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Original question:

ADS127L18: How many devices can be daisy-chained?

ADS127L18: connection to AM64

ERGIN AKGUEL
Prodigy 225 points
Part Number: ADS127L18
Other Parts Discussed in Thread: , ADC-PHI-PRU-EVM, SYSCONFIG, ADS8598H

Tool/software:

Hi,

we have a custom AM64 board where we would like to add the ADS127L18 converter. We have brought out a couple of pins from the ICSSG0 to a header which we can use, but we are not sure which pins exactly are needed to use this ADC converter with the 8 bit parallel mode.

Since we saw that there is the ADC-PHI-PRU-EVM (for am64evm) in combination with the ADS127L18EVM-PDK, this should be possible. I have checked the pins that are routed from the ADS127L18 via the adapter board to the am64, but some of the pins used are missing on our header.

I also checked the Sysconfig for the AM64 in the PRU-IO/ADC section where it shows the pin configuration for a couple ADCs (e.g. ADS8598H) with 16bit parallel interfaces, but the pins don't really overlap with the ADS127L18EVM-PDK/ADC-PHI-PRU-EVM configuration.

Now, there are a couple of questions which we have:

 

1. Is there a software example for the AM64 using the ADS127L18EVM, or will there be one in the future? (from that I could see how the pins are selected/configured)

2. Is it possible to change the pins freely in the ICSSG0 to fit the ADS127L18 8 bit parallel interface e.g. to our custom header?


p.s. maybe this needs to be moved to the processor/AM64 forum

Best regards,
Ergin

  • +1
    TI__Mastermind 48660 points

    Hello Ergin,

    As of today, we do not have plans to create example code specifically for the AM64.  However, using the ICSSG0, the AM64 should be able to interface directly to the ADS127L18 frame-sync data port.

    Regarding question 2, the processor/AM64 team will need to answer.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • +1 in reply to Keith Nicholas
    TI__Expert 7395 points

    Hi Ergin, 

    For question 2, the pins used in the existing examples are simple PRU GPIO pins that are programmed as either GPO to generated required signal output (by programming the PRU R30 register) or as GPI to receive the data on them (read on the PRU R31 register).

    If the pins that you have brought out on your custom header are GPIO pins of the PRU core, then you are free to choose the direction using sysconfig and how to use them as I/O pins by writing the required code for the PRU core.

    PRU-IO > ADC section of syscfg has features specific to certain ADCs, to create custom requirements TI Drivers > PRU (ICSS) > PRU (ICSS) GPIO section can be used to assign the pins to desired configurations.

    Regards,

    Nitika