AFE7225: DAC Powerdown Output Compliance

Part Number: AFE7225



I have been going through the design of the AFE7225 into my system and was wondering if the stated output voltage compliance is valid when the DACs are powered down (through register 0x207).

I have been planning to implement a resistive divider load network pulled up to 5V as recommended in the data sheet and app note SLAA399, however these examples seem to violate the compliance range (AVDD +/- 0.5 V) when the DACs are not powered on. For example, in SLAA399 figure 6, when the DACs are powered down (no DC bias) the pin voltage would be 3.8 V, which is outside of compliance range.  In my current design the voltage would be 4 V at the pins when turned off (similar the app note). Of course, once the DACs are turned on and bias current starts the voltage will return to the compliance range.

Overall I was wondering if this is expected and we only need to worry about the compliance range when the DAC is powered on, or if this is an incorrect way of biasing the DACs?  

  • To add some additional clarity, the datasheet mentions the following:

    • Register 0x103: "TX_DIS – Disables the digital signal chain of both channels in TX . All blocks in digital signal chain are powered down, and the output is DAC mid-code. Note: the DACs are not powered down in this mode." So in this disable/powerdown state it appears that the DAC remains in mid-code which maintains the expected bias voltage on the output
    • Register 0x207: "REG_PDN_TX : Power downs transmitter i.e both the DAC’s." In this state (as well as other PDN states) it does not specify what state the DAC are in (are they mid-code as well?)

    So the original post is really asking the following:

    1. In the various powerdown modes, do the DACs always remain at mid-code or is there a state where the DACs are actually powered down and pull no current into either pin?
    2. If the DAC is totally powered down, can the I/Os handle the larger voltage that is generated from the resistive divider network?
  • Brady,

    The pins cannot have a voltage applied to them at any point that is above the abs max rating or they will be damaged.



  • Yes, I get that the pins can't exceed the max rating, although the datasheet does not seem to specify a max rating for the DAC output pins (page 9).

    This previous thread seems to corroborate what my initial comment was referring to with regard to register 0x103 ( essentially saying that the DACs are by default at mid-code. 

    My only confusion is that when the DAC is "off" (could be via global powerdown from the PDN pin, register 0x207 which claims to shut down most circuitry inside the chip), is if the DAC is still at mid-code (as is the case with register 0x103) or are the outputs totally shut off and no current is pulled into either pin.

  • Brady,

    You are correct in that it doesn't specify a max rating for the DAC output directly but it cannot exceed the AVDD3 abs max value which is 3.6V.

    It appears that the DAC output is still on with a current draw to hold the output at mid-code.