AFE5809: LVDS sharing and data rate after Decimation

Tool/software:

Hi Team,

Question 1

When ADC directly drive LVDS output pins, that is, Digital Demodulator is bypassed, each input channel can drive its corresponding LVDS pair and data rate on LVDS pair is Fs * 14 bps, where Fs is sampling frequency and with 14bit per sample.

Further, Data from 8 input channels can also output from 4 LVDS pairs, while data rate on each LVDS pair doubles, that is up to  Fs * 14 * 2 bps.

The LVDS sharing rule is

Ch1 + ch2    to  LVDS3(D3P/N)

Ch3 + ch4    to  LVDS4(D4P/N)

Ch5 + ch6    to  LVDS5(D5P/N)

Ch7 + ch8    to  LVDS6(D6P/N)

Is the above right?

Question 2

I prefer less PCB routing and I do NOT want a higher data rate on the LVDS. So I decide to use the Digital Demodulator. When using Digital Demodulator, every 2 input channel can also share 1 LVDS pair. But sharing rule seems to change as follows

Ch1 + ch2    to  LVDS1(D1P/N)

Ch3 + ch4    to  LVDS3(D3P/N)

Ch5 + ch6    to  LVDS5(D5P/N)

Ch7 + ch8    to  LVDS7(D7P/N)

And what I care most is, CAN I achieve a significant decrease of data rate with a large decimation factor M ?  That is, only effective down-sampled data is transmitted through the LVDS line.

e.g.   ( Fs /M ) * 2 * 16 * 2

where  ( Fs /M ) is the equivalent sampling rate after decimation, * 2 (I/Q 2 data per sample), * 16 (16bit per I and Q data), finally * 2 represents 2 adjacent channels sharing the same LVDS pair.

Is that right?