Other Parts Discussed in Thread: LMK04828, LMX1204EVM
Tool/software:
My team has set up a system using two of your ADC12DJ5200EVM boards connected to a Xilinx VCK190EVM board over the FMC buses to do concurrent sampling of 2 analog inputs at a 10Ghz rate. We have used your ADC12DJ5200RFEVM GUI SW to configure each of the boards for External Clock, 5000Mhz External Fs Selection, JMODE30, No Sync Input Signal. We are driving the DEVCLK (j10) input to each board with 5.0Ghz and the External Reference Clock input (J17) with 250Mhz. Both input clocks are locked to a 10Mhz reference.
The system is operating fine in subclass #0 mode, no concurrent sampling and no ADC synchronization or deterministic latency. Our concern is subclass #1 mode. Everything we read about synchronizing multiple ADC's implies that each ADC must receive the same SYSREF. Some articles even state that trace lengths must be matched so that each ADC receives EXACTLY the same SYSREF.
That is hardly the case in the system that we have implemented. In our case each ADC receives the SYSREF generated by the LMK04828 chip on its board. The two SYSREF's can be out of phase with each other, and the phase difference will vary from power cycle to power cycle. However, the phase difference is not totally random, they are always out of phase by an integral number of 250Mhz clock cycles. That integral number varies from 0 to 31 and has been verified by looking at the two SYSREF's with a scope. The SYSREF divisor is set to 32.
Is such a system capable of operating as one would design in subclass #1 with deterministic latency and doing concurrent sampling with the two ADC boards? Or do we have to use the SYSREF_SMA input to the board (J2) and drive it with a 250Mhz/32 clock locked to the 5GHz and 250Mhz clocks?
Additionally, we are wondering if it is possible to do concurrent sampling with two copies of the ADC board at all. The datasheet has a sentence that says, "In order to maintain timing alignment between converters, stable and matched power-supply voltages and device temperatures must be provided". It would seem that the two ADC's would need to be on the same board and probably connected to the same heatsink to meet that requirement.
Finally, one question about SYSREF calibration. It seems like this is a useful feature, but not so good for subclass 1 applications which require concurrent sampling. SYSREF calibration adjusts the tAD value for each ADC and could adjust them very differently. If they are adjusted differently that makes the sampling point for each ADC a different instant of time, which is the opposite of what is needed for concurrent sampling. Is the recommended technique for concurrent sampling to adjust the timing of SYSREF to the ADC with the LMK04828 chip rather than to use automatic SYSREF calibration? Or is the recommended technique for concurrent sampling to go ahead and do automatic SYSREF calibration and if the results are close enough just adjust the result in each ADC to the average of the two calibrations results so they are the same in both ADCs?
