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ADS127L21: ADS127L21: AC voltage measurement

OMER SARI
Prodigy 20 points
Part Number: ADS127L21

Tool/software:

Hello,

I have a few questions about the ADS127L21.

1) Was it written in the evaluation board datasheet and the ADS127L21 datasheet that internal clock is not recommended for AC voltage measurement. But we tested it with the evaluation board using a unipolar signal of 500mV AC with a 1.65V DC offset. we readed this signal. In what situations is this expression valid for AC voltage. When measuring a 1.65VDC offset and a 500mVAC signal, would we encounter any unexpected ADC AC voltge measurement with internal clock.

2) Do we need to measure the clock when applying an external clock to the ADC? Do SCLK and the external clock need to be synchronized? Because the datasheet states the following: 'Minimize phase skew between SCLK and CLK (< 5ns)'. I didn't fully understand this statement, what is the reason for it?

I would appreciate a quick reply.

thank you

  • +1
    TI__Mastermind 41010 points

    Hello Omer,

    The ADS127l21 internal clock jitter is high enough to degrade SNR for input frequency greater than about 10Hz.  If your system noise requirements can tolerate the increased noise, then you may be able to use the internal clock.  The primary purpose of the internal clock is for DC measurements, where the bandwidth is less than 10Hz.

    Take a look at TI Precision labs that discusses the effects of clock jitter and noise:

    https://www.ti.com/content/dam/videos/external-videos/en-us/8/3816841626001/6242062186001.mp4/subassets/adcs-sar-delta-sigma-noise-and-drive-considerations-presentation.pdf

    Below is a 2kHz input signal, first plot using an external clock with low jitter (~50ps rms) and second using the internal clock:

    The SNR is now reduced quite a bit.  Again, for DC signals up to 10Hz, the reduction in SNR is not significant, but at 2kHz, there is a much larger reduction in SNR, or about 10x higher noise levels.

    You do not need to measure the external clock, but the external clock will determine the output data rates of the ADS127L21.  SCLK and CLK do not need to be from the same clock source for operation of the ADC, but if different clock sources are used, there will be additional noise created by the mixing of the clocks to lower frequency.  For best performance, we suggest using the same clock source, but it is not necessary in many cases.

    Below are the ADS127L21 results with a 2kHz input sinewave where both CLK and SCLK (both set to 32.768MHz) are derived from the same clock source:

    Same exact conditions, but CLK and SCLK are generated by two different clock sources:

    These additional clock spurs are very low magnitude, and do not degrade SNR or THD, but they do increase the SFDR noise floor if this is important.

    Regards,
    Keith Nicholas
    Precision ADC Applications