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ADC3664: Reduce clock pin

ttd
Mastermind 8120 points
Part Number: ADC3664

Tool/software:

Dear Technical Support Team,

I'd like to use six ADC3664 on the same board and it has four clks.

Do you have any idea to reduce or sharing clocks?

CLK  (in )

DCLKIN(in)

DCLK(out)

FCLK(out)

According to previous post, it seems to reduce and sharing clocks.

Is it correct?

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1388138/adc3664-sharing-dclk-fclk?tisearch=e2e-quicksearch&keymatch=ADC3664

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1173059/adc3663-clock-inputs-for-sample-clock-clk-dclkin?tisearch=e2e-sitesearch&keymatch=ADC3663%20DCLKIN#

Best Regards,

ttd

  • 0
    TI__Mastermind 27560 points

    Hi TTD,

    TI probably has a clocking device that can be used to drive the sampling clock and DCLKIN for all six devices. If you need more information on this please let me know.

    But you would still need to route all these clocks to each of the six ADCs.

    For the DCLKOUT and FCLK, you need to bring each of these to the FPGA from each ADC unfortunately.

    Have you looked into one of our quad or octal devices that might help here to reduce the number of clocking requirements?

    Thanks,

    Rob