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ADS131M02: AVDD and DVDD Filtering/Impedance Matching

Will Mcknight
Prodigy 20 points
Part Number: ADS131M02

Tool/software:

Hello,

I was hoping you could help inform me on the best approach for filtering the supply rails given me application, as well as impedance matching advice. I don't have much experience with ADCs, let alone high bit count ADCs.

We have many cascaded stages, but below summarises what I am dealing with,

125Vrms AC input -> bucks down to +24VDC -> bucks down to +5VDC -> LDO's to 3.3VDC

The 3.3VDC is being used for AVDD as well as DVDD.

  1. If I want to decouple AVDD from DVDD using an LC filter (inductor not ferrite), how should I go about choosing the cutoff frequency so that I'm not exciting any resonances as well as not impeding power flow into the pin for ADS131M02
    1. Which frequency in the datasheet should I be designing around?
  2. Should I be placing the LC closer to the AVDD or DVDD pin?
  3. For my voltage measurement of AC line, i'm using a standard AC line voltage divider with an anti-aliasing filter near the ADC AIN pins. Should the effective resistance of the divider be equal to the differential input impedance of the pin (300k)? PGA = 1.
  4. For my current measurement I'm using a CT, so same relative question above but should the output impedance plus the burden resistor equal the input impedance of the AIN pin?

Cheers!

  • 0
    TI__Mastermind 38235 points

    Hi Will,

    Welcome to the E2E forum. Please see the answers below.

    1&2. There is no need to use a LC filter on the power supply as long as you use a noise and high PSRR LOD, like TPS7A4700 which is often used on our EVM boards. Only a capacitor for each power supply pin is recommended for the ADC, the capacitor should be placed close to the ADC, you can check the schematic in the ADS131M04EVM user guide. 

    3. No need to match the impedance, you can see 9.2.2.1 Voltage Measurement Front-End section in the ADS131M02 datasheet for the details and example how to select a resistor voltage divider.

    4. No need to do that. you can see 9.2.2.2 Current Measurement Front-End section in the ADS131M02 datasheet for the details.

    You can also see the voltage and current measurement circuit in some reference designs: 

    Regards,

    Dale

  • 0 in reply to Dale Li
    Prodigy 20 points

    Hi Dale, 

    Thanks for the speedy response, it is appreciated.

    But, for my own learning, let's say hypothetically the PSRR is not great and noise is getting onto the output of the LDO. Can you then explain 1&2?

    for 3&4 the reason you don't need to is because the charged cap parallel to the pin is holding the sample, and is extremely close to the pin so the transmission length is tiny compared to the electrical wavelength?

    Can you explain " the common point being connected to GND instead of using one burden resistor for best THD performance. This split-burden resistor configuration ensures that the waveforms fed to the positive and negative terminals of the ADC are 180 degrees out-of-phase with each other". Why does having the split burden resistor ensure the positive and negative pins of the ADC are 180 deg out of phase?

  • 0 in reply to Will Mcknight
    TI__Mastermind 38235 points

    Hi Will,

    See the feedback below.

    1&2: Regarding your assumption, you need a filter on the power supply. The cutoff frequency depends on the noise and transients observed on your power supply. You can find ADS131M02's PSRR specification from the datasheet, it is around 88dB rejection at DC and 78 dB rejection for 50Hz or 60Hz frequency. The more noise or transients you can filter out, the less error will be seen in your code. Unfortunately the datasheet does not have a graph of PSRR vs frequency. However, it is very worth using a low noise LDO as the AVDD power supply to the ADC. 

    3&4: When AINxP and AINxN pin of the ADC are connected to the secondary output of CT, each pin will have a signal with an opposite phase corresponding to the ground (GND). The split-burden resistor configuration ties one lead of the resistors to GND, such a configuration can guarantee both signals have completely opposite phase if the burden resistors have the exactly same value. Below is a simulation example I just did in TI-TINA, the phase difference between the signals on AINxP and AINxN after the burden resistors is exact 180 degree. The split-burden resistor configuration is usually used for differential measurement since the ADC measures the voltage difference between AINxP and AINxP. The split-burden resistor configuration can also lead to less offset and harmonics so the best THD performance can be achieved.

    Regards,

    Dale