Tool/software:
Hello,
I have two questions regarding the amplitude of the sampling clock signal.
We want to drive the sampling clock signal with an FPGA. Since we have a few inches of trace between driver and receiver, we need to terminate the signal. We quickly run into issues with the maximum current of the FPGA IOs (if using standard 50 ohm termination), or require high impedance traces that are harder to manufacture. The typical amplitude is listed at 1Vpp, but there are no minimum/maximum. We might be interested in using AC-coupled differential LVDS signals to drive the sampling clock, allowing us to use 100 ohm differential traces and achievable FPGA IO current. This seems to be supported based on the graph below.
My questions are the following:
1) What is the mechanism explaining how sampling clock amplitude affects the signal quality? Is it because lower clock amplitude increases the triggering jitter which increase noises on a sinusoidal waveform? I ask this question because we plan to sample a square wave signal and we are able to sample away from the edges. That makes our application more robust to triggering jitter than sampling a sinusoidal signal which constantly changes.
2) Can the amplitude range listed above be considered "recommended values"? What I mean by that is that if we accept the performances at 0.5Vpp, is it a sustainable/glitch-free/repeatable operating point? The fact that the datasheet does not mention a minimum amplitude signal makes me wonder.
Based on your answer we will be able to decide if using LVDS is a viable solution.
Best regards,
Vincent