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ADS8167: datasheet discrepancy (rev D (Jun 2024) vs. rev C (Oct 2019) in SPI timing diagram.

Ben Kim1
Prodigy 10 points
Part Number: ADS8167
Other Parts Discussed in Thread: ADS8166

Tool/software:

I just noticed that there was a newer datasheet for ADS8167 (Rev D, June 2024). 

I compared it with Rev C (Oct 2019) just in case. We designed our board based on Rev C datasheet.

I can see that the newer version has better document structure, but I  also notice that the SPI timing got changed (e.g., fig 6-21 (new, rev D) vs. fig 53 (older, rev C).)

Which one is correct?  Even though the newer timing diagram looks cleaner and bigger, I think the old one might be correct and the new one doesn't make sense to me in that I cannot see how I can bring in the MSB without any SCLK edge.  Can you clarify this, please?

PS: I wanted to upload those two TI datasheets (rev C and rev D), but this post doesn't seem to allow me to do that... // oh, just drag the file into the edit area.  here we go.

ads8166_8167_8168_SAR_ADC_8-chan_16-bit_250ksps_500ksps_1Msps_SPI_32-VFQFN_SBAS817C_nov2019_ti_p97_.pdfads8166_8167_8168_adc_16-bit_1Msps_500ksps_250ksps_8-chan_SAR_SBAS817D_jun2024_ti_p86_.pdf

  • 0
    TI__Mastermind 40490 points

    Hello Ben,

    Welcome to the TI E2E community.

    The ADS816x is compatible with all SPI modes, but works a little bit different.  In the case of SPI mode 00, the MSB is launched on /CS falling edge (normal behavior), but the rest of the bits are launched on the SCLK rising edge (typical operation would be to launch remaining bits on SCLK falling edge).  In both cases, you capture data on the rising edge.

    The ADS816x specifies a hold time of 2.5ns, which is compatible with most processors (many do not require any hold time, or a hold time of 0ns).

    The new rev D datasheet attempts to show the actual behavior of the ADS816x.  

    SPI mode 00:

    MSB launched on the falling edge of /CS (RED) (Normal SPI behavior)

    All other bits launched on the rising edge of SCLK (RED) (early launch of data, normal SPI behavior would launch data on SCLK falling edge)

    MISO on host controller should capture data on the rising edge of SCLK (BLUE) (Normal SPI behavior)

    The ADS816x launches data 1/2 clock edge early to support higher SCLK frequency; prop delay is up to 19ns.  If SCLK launch edge was falling edge, then maximum SLCK frequency would be limited to about 25MHz, but since the ADS816x launches on the SCLK rising edge (and the host controller captures on the SCLK rising edge, the prop delay can be nearly the same time as the SCLK period, which then supports SCLK frequency up to 50MHz).

    I think both datasheets are correct, but it can be confusing since the ADS816x does not behave like a standard SPI due to the early 1/2 clock launch of data.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 10 points

    Dear Keith,

    Thanks for your quick response and explanation on the 1/2 early clock issue of the device's SPI interface.

    After posting a question yesterday, I found that the Rev D datasheet added a couple of new timing diagrams in fig 5-1 and fig 5-2 (both on page 11), which weren't in Rev C datasheet.

    Maybe while trying to explaining  or emphasizing the early 1/2 early clock issue, Rev D's figure 6-21 and 6-22 (both on page 37) altered the Rev C's figure 53 and 54 (both on page 40).  They look different and both cannot be correct at the same time, I think.

    At any rate, I will use your advice on early 1/2 clock issue and the new timing diagrams in figure 5-1 and 5-2 to devise the SPI required of ADS8167.

    Best Regards,

    ADS8167_revD_timing_on_page11_2024_08_02_.pdf