Other Parts Discussed in Thread: ADS5474
Tool/software:
I'd like to know how to use the DRY to catch the data.
Could you provide FPGA RTL codes related to the DRY?
Now I am using the RTG4 made by Microchips.
Regards
Jae-Heung Yeom
The datasheet reads:
Referencing Figure 1, the polarity of DRY with respect to the sample N data output transition is undetermined
because of the unknown startup logic level of the clock divider that generates the DRY signal (DRY is a
frequency divide-by-two of CLK). Either the rising or the falling edge of DRY will be coincident with sample N and
the polarity of DRY could invert when power is cycled off, on or when the power-down pin is cycled. Data capture
from the transition and not the polarity of DRY is recommended, but not required. If the synchronization of
multiple ADS5474 devices is required, it might be necessary to use a form of the CLKIN signal rather than DRY
to capture the data.
