Tool/software:
Dear all,
we are starting TI-JESD204-IP (1.11) evaluation with Vivado 2019.2 simulator. The simulation of zc706 unmodified example works fine, using the loopback, we can see data sent to be also received. Then, a small modification was done to use just 1 MGT lane and 12bit DAC/ADC data and the loopback simulation showed also the data to be passed correctly.
Now, we need to change the part from z7045 to z7030. Both are GTX transceivers. I followed the guide and re-created the GTX wrapper using the transceivers wizard for z7030 part with the same settings. During simulation start-up, error message pop-up that gt0_rxchariscomma_out port on gtx_8b10b_rxtx instance does not exist. If I comment out this port assignment (// .gt0_rxchariscomma_out (gt0_rxchariscomma_out),), the simulation compiles successfully.
Unfortunately, the rx_lane_data_valid is not triggered anymore and rx_lane_data are not updated anymore. The tx_lane_data are toggling as expected.
Can you help with gt0_rxchariscomma_out issue if this can be the cause for data not receiving? Or how to proceed further... I can send the design or waves if needed.
Thank you,
Michael
