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ADS127L01: Settling time and group delay

Rachel Collins
Prodigy 10 points
Part Number: ADS127L01

Tool/software:

Hello, 

I am working on a system where multiple devices with ADS127L01's are using the same clock and trigger source for MCLK and START respectively. MCLK is running at 16 MHz and I'm using an OSR of 32 for a sample rate of 62.5 kHz. I am measuring the phase response of a single device and have some questions about the phase response of the wideband filters on the ADS127L01. 

1. When using SPI mode, the sequence for starting a measurement is START pin goes high, 84 conversions take place, then DRDY goes low to signal data is available to be read from the DATA register. What conversion number is the data that is read in the first SPI transaction from? 

2. What group delay will I see in my phase response measurement if I am resetting the ADS127L01 between each acquisition and using the START pin to trigger each acquisition? From the datasheet, it looks like if the ADS127L01 is used in free run mode, the group delay of 42/Fdata would be seen, but starting an acquisition from a START command or START pin trigger results in the settling time of 84/Fdata being the group delay that would be seen in the phase response measurements.

  • +1
    TI__Mastermind 41090 points

    Hello Rachel,

    Welcome to the TI E2E community.

    When you set START pin high, the digital filter initially is in a reset state, and then 'slowly' settles to the sampled input value.  The /DRDY is held high until the filter is fully settled.  The first reading that you will get over SPI after /DRDY goes low will be the most recent conversion reading, or the 84th reading in the case of the wideband filter.  The digital filter inside the ADS127L01 behaves similar to using a zero-latency SAR ADC with an analog input filter.  If you apply a step input to an input analog filter with a large time constant relative to the sample period, the first several readings from the SAR ADC will not accurately represent the input voltage.  The ADS127L01 suppresses these initial readings to allow the digital filter to settle.

    Since you are using the START pin to control the overall conversion rate, the group delay will effectively be the full latency of 84 conversion cycles.  Your effective sample rate will not be 62.5kHz, but 62.5k/84=744Hz.  (I assume you are using an OSR of 256, not 32, to get 62.5kHz using MCLK=16MHz.)  This means the maximum input frequency you can sample in this mode without aliasing will be 744/2=372Hz, or the Nyquist rate.  Note that in this mode of operation, the wideband filter will still pass any input signal frequency up to about 1/2 the conversion rate (1/2*62.5kHz=31.25kHz).  This means any input frequency between 372Hz and 31.25kHz will be aliased with 0dB of attenuation, defeating one of the key advantages of the wideband filter.

    If you need to use the START pin to control the overall data rate, then I would suggest using the low-latency filter.  Since the low-latency filter settles in much less time (Table 3 for exact times), you can use a higher OSR setting to get the same effective data rate as the wideband filter, resulting in lower noise and higher SNR.

    Regards,
    Keith Nicholas
    Precision ADC Applications