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ADS131M04: Data returned from ADC abnormal

Frank QIN
Expert 7300 points
Part Number: ADS131M04

Tool/software:

Hi Team,

When we are doing a BCI test, insert interference to the AD sample side, we found the SPI read back from ADC is not correct. At this stage, we only started to configure the ADC, so only write and read the register 01h, 02h, 03h. We assume the DRDY shouldn't be ready at this stage.

One of the risks we have found is the CS pin tied to GND, might disturb the SPI.

Here is the comparison table between OK part and fail part. We write with SPI and then read back the registers.

OK part Fail part
STATUS register 1 0x00  0x00 0x00（MCU sent to ADC）
-> 0x05 0x0F 0x00 （ADC sent to MCU）		 0x00  0x00 0x00 -> 0x00 0x00 0x00
Clock register 2.1 0x61 0x80 0x00 0x0F 0x16 0x00 -> 0x05 0x0F 0x00 0xFF 0x9E 0x78 0x61 0x80 0x00 0x0F 0x16 0x00 ->  0x00 0x00 0x00 0xE1 0x39 0x00
2.2 0xA1 0x80 0x00 -> 0x41 0x80 0x00 0xA1 0x80 0x00 -> 0x00 0x00 0x00
2.3 0x00 0x00 0x00-> 0x0F 0x16 0x00 0x00  0x00 0x00 -> 0x00 0x00 0x00
Mode register 3.1 0x61 0x00 0x00 0x05 0x10 0x00  -> 0x05 0x0F 0x00 0xFF 0x9E 0x7B 0x61 0x00 0x00 0x05 0x10 0x00  -> 0x00 0x00 0x00 0xE1 0x39 0x00
3.2 0x61 0x00 0x00 0x05 0x10 0x00  -> 0x1C 0x27 0x20 0x00 0x00 0x00

There are numbers of devices show this kind of failure, we don't think it is a single failure It should be relate to some interference on SPI or digital error inside the ADC.

Could you please share some insight on this case and advise how should we investigate next step?

Thanks

Best,

Frank

  • 0
    TI__Mastermind 40870 points

    Hi Frank,

    Is the customer able to get communications working reliably under normal conditions (no BCI)?  Since /CS pin is permanently tied low, any small amount of noise or glitch on the SCLK pin will result in the SPI communications failing.  Running BCI tests on any cables connected to the board, including the analog inputs, can couple noise into the board that can result in glitches on the SCLK pin.

    Please try to capture the SCLK signal directly at the ADC SCLK pin using an oscilloscope to see if this signal has any glitches.  You may need to add filtering directly to the SCLK input (a series resistor of 50ohm up to 100ohm usually works well).  However, if the noise coupled into the board is high enough, you may also need to change the board layout to improve performance.

    The customer may need to provide additional input protection; the below application note shows how to do this for the ADS131M0x family.

    https://www.ti.com/lit/an/sbaa506/sbaa506.pdf

    In any case, since /CS is tied low, the software should be written to recognize when communications has failed, allow for a SPI timeout (default on power-up) and then resume communications.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    TI__Mastermind 40870 points

    Hi Frank,

    For best performance and better immunity to electrical transients/noise, I highly recommend the customer use the /CS pin.  In this case, if there is a glitch on the SCLK line, only the current SPI frame will be corrupted, and any following SPI frames will continue to work.

    Regards,
    Keith