Tool/software:
Dear TI,
I have a question about ADCs and the potential metastability issue. Specifically, I'm concerned about the internal comparators in the ADS61B49 architecture.
Could metastability in these comparators trigger the OVR_DSOUT pin (which is used as an overflow output in our case)? For example, could metastability cause the logic to incorrectly interpret a sample as being out of range, potentially leading to a false overflow error? We use this pin to trigger an FPGA for critical error detection, and I am worried that metastability might cause false OVF errors.
If this scenario is possible, we may need to implement some filtering within the FPGA as a workaround.
Additionally, we are unclear about the exact logic behind the OVR_DSOUT pin. Once it is triggered, when does it get reset?
Thank you in advance for your assistance.
Best regards,