Tool/software:
Hi,
There is PLL lock issue and JESD issue.
Could you guide how customer can debug this issue? how they can approach this issue?
After power up sequence, below is register status.
To solve this issue, FPGA JES204B TX IP setting and clock is modified but DAC clock is not changed.
Last status is as below.
nSYNC pin is high and there is no Sync Request.
It seems to not work for Serdes due to PLL unlock.
Thanks.
