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ADS8588S: How to use only 4ch

ttd
Mastermind 8050 points
Part Number: ADS8588S

Tool/software:

Dear Technical Support Team,

In order to read data from the ADS8588S for 4 channels only (ch1 to ch4), even if I assert only CONVSTA, BUSY does not go High and I cannot read any data (CONVSTB is fixed at '0').
I thought this method could be done by checking with E2E below.

-------------------------------------------------------
Q1
The ADS8588S is equipped with an 8-channel ADC, but when reading only 4 channels (ch1 to ch4) in Read After Conversion, assert only “CONVSTA Data Read Operation Timing Diagram” and 'Figure 4: Parallel Data Read Operation, CS and RD Separate Operation, CS and RD Separate'. (CONVSTB is fixed at '0' and not used)

Answer

For Q1 - yes, that is correct.  Read after conversion is done once BUSY is asserted low.

e2e.ti.com/.../ads8588s-questions-about-read-after-conversion
-------------------------------------------------------

It seems that if a signal is input to CONVSTB with a repeating rising edge every 5us cycle, the same as CONVSTA, BUSY will go High and read will start.

■Questions

(1) To read data for 4 channels (ch1 to ch4) with the ADS8588, is it not enough to assert only CONVSTA?
    Could you tell me about the method of reading only for 4 channels? 

　I would like to confirm if I am using the method to read only 4ch incorrectly.


(2) If CONVSTA and CONVSTB must be asserted even for 4 channels, can I do by setting CSn and RDn High at the timing of AIN_4 Data as shown below?

■Condition
Settings on may system is below.
・CONVSTB is fixed at '0' and not used.
・Read After Conversion
・Parallel Data Read( CS and RD Separate)
・Refer to following timing.

“Figure 2. Data Read Operation Timing Diagram”
‘Figure 4: Parallel Data Read Operation, CS and RD Separate’.

Best Regards,

ttd

  • 0
    TI__Guru**** 174266 points

    Hi ttd,

    For new Q1, How do you have the OSR pins set?  If you are oversampling with the ADS8588S, then both CONVST signals must be toggled.  For Q2 - Yes, you can short cycle the data read and only take the first four conversion results.

  • 0 in reply to Tom Hendrick
    Mastermind 8050 points

    Hi Tom,

    Thank you for your reply.

    OS[2:0] is set from FPGA at “000”, so it is in No oversampling mode, but unless both CONVSTA and CONVSTB are toggled, BUSY is High and Read data is not output. 

    Also, I was able to read from the ADC by inputting a signal in a control similar to the waveform of Q2, but sometimes an unintended value is read irregularly. It checked AMD FPGA's internal circuit via Signal Tap(like Logic Analyzer) . So I'm investigating about it about either ADC or FPGA logic.

    Best Regards,

    ttd 

  • 0 in reply to ttd
    TI__Guru**** 174266 points

    Hi ttd,

    I got ahold of the design team and they told me that the behavior you are seeing with BUSY is to be expected with the 8-CH ADS8588S.  If only one CONVST goes active, the BUSY will not fire off.  That being said, they tell me that the four channels of Ax should still convert and be readable after waiting through the MAX conversion time period.  Let me know what you find out about the 'unintended value'.