TI-JESD204-IP:rx_lane_valid signal are transition from ‘1’ to ‘0’

Hi,

These errors can either be due to any of the following:

1> the Tx and Rx frame alignment going out of sync (frame/multi-frame errors)

2> signal integrity issues on the board, which can cause all forms of mismatches at the receiver.

3> the reference clocks to the FPGA are drifting (does the FPGA get its clocks from the same root source as the ADC)?

4> it can also be timing related, which worsens as the FPGA temperature rises. Kindly check your timing constraints

One option will be to try running the link at a lower rate to see if the problem still occurs. That may give some indication about signal integrity or timing related problems.

Regards,

Ameet

Hello, Ameet.

Thank you for your advice.

I found something new.

Noise was observed on the PD-pin of ADC09SJ1300 when IP-Errors occurred and the rx_lane_valid of JESD-IP became low.

We are investigating whether this noise is coming from on our board or something else.

Have you experienced similar errors in the past?

Thanks

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CH1(yellow): PD-pin (Pull-down at 470KΩ on our board)

CH2(green): rx_lane_valid

CH3(blue): PLLREFO+ (312.5MHz)

Hello, Ameet.

Thank you for your advice.

1> the Tx and Rx frame alignment going out of sync (frame/multi-frame errors)

Do IP-Errors mean that the Tx and Rx frame alignment going out of sync?

2> signal integrity issues on the board, which can cause all forms of mismatches at the receiver.

I'm checking the signal integrity of 4Lanes by eye diagrams using Xilinx IBERT module and it looks okay.
Is there any other easy way to check?

3> the reference clocks to the FPGA are drifting (does the FPGA get its clocks from the same root source as the ADC)?

Clocks are from same root. MMCM of FPGA generates Clocks.
Clocks are:
・625MHz (dividing from 625MHz to 312.5MHz) ->for ADC CLK
・125MHz -> for JESD-IP
・62.5MHz -> for JESD-IP
・0.625MHz -> (dividing from 125MHz to 0.625MHz) for ADC sysref
・156.25MHz ->for FPGA internal

4> it can also be timing related, which worsens as the FPGA temperature rises. Kindly check your timing constraints

What are the strict timing constraints?
Where should I check on the data sheet?

Thanks

Hello, Ameet.

> One option will be to try running the link at a lower rate to see if the problem still occurs. That may give some indication about signal integrity or timing related problems.

If we test at a low rate and there is no problem, which is more likely to be the cause, signal integrity or the timing?

We have tested the following settings and the problem appears to be less likely to occur.
ADC: ADC09SJ1300, 800Msps, JMODE10 (2Lane), LineRate is the same 5 GHz.

Do we need to lower the LineRate as well?

Thanks