Hi,
The reset value of the SPI_CRC_DAT register is zero.
The CRC is automatically reset when CSB or DRDYB is de-asserted.
This means the SPI_CRC_DAT register will reset back to zero if the ADC data (registers 0x1A, 0x1B, 0x1C) is read on a separate SPI frame prior to reading the CRC value.
The CRC value should be read in the same SPI frame immediately after the ADC conversion data registers.
Conveniently, the SPI_CRC_DAT register address is located next to the ADC_DOUT register address so that the CRC value can be easily read as part of the data set.
Simply write 0x3 to the SZ field and send clocks to do a 4-byte read (streaming mode) starting at the 0x1A address, before de-asserting CSB.
