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Interface ADS6243 with Xilinx V5 LVDS interface

David Zhang16358
Expert 1860 points
Other Parts Discussed in Thread: ADS6243

The LVDS buffer of ADS6243 is powered by 3.3V but I have used 2.5V to power LVDS banks of V5 since I wan to use internal termination resistors.

if the common mode voltage of ADS6243 LVDS is 1.2V, Can the 2.5V receiver side  receive reliable data ?

  • 0
    TI__Mastermind 29220 points

    Yes, that would be fine.  On our TSW1200 the supply voltage for the bank of I/O that have the LVDS inputs are at 2.5V.  One nice thing about LVDS is that the signal definition is indepenent of the supply voltage of the LVDS device.  The LVDS signal is a nominal 350mV swing about a common mode of 1.2V, so it doesn't matter if the driver or the receiver has the same or different supply voltages.

    Regards,

    Richard P.