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ADS7142-Q1: ADS7142QDQCRQ1

Jim Wang
Prodigy 10 points
Part Number: ADS7142-Q1
Other Parts Discussed in Thread: ADS7142,

Tool/software:

our application requires the ADC (ADS7142) provides the i2c transaction continuous access with the same register address (we want to read the ADC sample data buffer) 

The datasheet does not appear to be clear when specifying the behavior of a subsequent read without again writing the register address illustrated in 7-26. If I had to guess, it may be required to perform this between each read of the ADC values.

but at page 33 of datasheet: Figure 55. Device Operation in Manual Mode shows, the float chart which shows the I2C READ transaction (format) to access the converter's data buffer

this I2C READ transaction format is different from the 7.3.11.1.1 Single Register Read

can you clarify what the I2C host need to provide to continuously access the converter's data register (same I2C register address) without needing to repeatedly specify the device ID and register address

  • 0
    TI__Genius 16870 points

    Hi Jim,

    If you would like to get data conversion in real time over the I2C bus rather than reading them from the data buffer, you can follow the process described in figure 7-13 of the datasheet. Here you do provide the "Read" bit I believe you are referring to by the "I2C READ transaction format". Conversion data will continue to be output on the I2C bus until the host sends a NACK to the device, indicating the device to stop conversions.

    Does this seem like it would work better for your application?

    Regards,
    Joel

  • 0 in reply to Joel Meraz
    Prodigy 10 points

    Hi Joel, it looks like you are confirming that the data buffer of ADC can be read continuously by I2C host if it provided the i2c transaction as: device ID -> Read Bit-> sample1->sample2->.......-> sampleN->NACK?

    what datasheet you are referred too? because I did not see the Figure7-13 in the datasheet I got on-line. can you send me the datasheet?

    Thanks

    Jim

  • 0 in reply to Jim Wang
    TI__Genius 16870 points

    Hi Jim,

    This figure is on page 31 of the datasheet available publicly. Let me know if you have any issues finding or accessing it.

    https://www.ti.com/lit/ds/symlink/ads7142-q1.pdf

    Regards,
    Joel

  • 0 in reply to Joel Meraz
    Prodigy 10 points

    Hi Joel, it is still not clear to me regarding the i2c frame for data buffer read shown in Figure 7-13. I'd a datasheet for ADS7142:  ADSSBAS773A –SEPTEMBER 2017–REVISED DECEMBER 2017

    it shows "Reading a Continuous Block of Registers" which requires two i2c frames to execute (see below capture). this is the i2c frames we are implementing for i2c sequential read currently in another I2C slaves. the difference is that the slave register address would be incremented when read back as a block.  My question is that would the first i2c frame required for the ADC data buffer i2c sequential read ?

  • 0 in reply to Jim Wang
    TI__Genius 16870 points

    Hi Jim,

    You're reading from the ADS7142 datasheet, not the ADS7142-Q1 datasheet. They will contain mostly the same information, but I am speaking in reference to the figures and page numbers per the Q1 version. 

    I will continue speaking in terms of the ADS7142-Q1 datasheet that I linked above. The manual mode conversions and autonomous mode conversions stored in the data buffer are not accessible through the register map, so none of the opcodes in table 7-4 apply to them. These opcodes work after providing the device with a WRITE bit (low) after the device's 7-bit I2C address has been provided. 

    Instead, the manual mode or autonomous mode conversions are accessible by providing a READ bit (high) after the device's 7-bit I2C address is provided. See figure 7-13 of the datasheet for reading conversion data in manual mode, or figure 7-8 for reading from the data buffer in autonomous modes. They are functionally identical. 

    Overall, it is important to keep in mind that conversions are not read from conventional registers available in the register map, so you should follow the procedure as described in figures 7-8 and 7-13.

    Regards,
    Joel