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Original question:

[FAQ] ADC128S102-SEP: Power on / off (up / down) sequencing requirements

ADC128S102-SEP: How to fulfill the condition VA > VD during power down

heino Smit
Prodigy 40 points
Part Number: ADC128S102-SEP

Tool/software:

When looking at figure 8-1 of the ADC128S102-SEP datasheet, I don't see how to fulfill the condition mentioned in section 9.1 Power-Supply Sequence in the same datasheet.
When powering down, VD will power down slower then VA due to the RC network of 51ohm and 0.1uF//1uF. In this case VD > VA which is not allowed. How to deal with this?

  • 0
    TI__Expert 6940 points

    Hi Heino,

    You are completely correct. VA should then be after the resistor, and VD should be before the resistor. This is likely an oversight in the typical application circuit.

    Regards,
    Joel

  • 0 in reply to Joel Meraz
    Prodigy 40 points

    In that case you will have a forbidden situation during power on, VD will be larger then VA which is not allowed. Also the filtering of VA will be meshed up since VD is directly to the clean supply.

  • 0 in reply to heino Smit
    TI__Expert 6940 points

    You're correct. My suggestion would still have an issue on the power-on cycle...

    The rationale behind why VD must not exceed VA by more than 0.3V is that there is a protection diode going from VD to VA. If the current through this diode exceeds 10mA, it is in danger of being burnt out.

    Here is where I have to go against the FAQ you included, which states that VD must never be 0.3V above VA. If VA and VD share a supply, and VA ramps up before VD during power-on, then it will also ramp down before VD ramps down at power-off, technically violating the absolute maximum rating. It might not be practical to never violate the absolute maximum specifications in a design.

    It will be difficult to ensure VD never exceeds VA on both the power-on and power-off cycles, therefore, it must be ensured that the current through the diode does not exceed 10mA. The behavior of the power supply when powered off would be important to consider. It could be floating or tied to GND when powered off. If it is shorted to ground, the current through the ESD diode could exceed 10mA. If it is floating, then likely little current will flow if at all.

    Another factor to consider is just how long the current will be flowing for. At power-off, any current that flows through the diode will only be for short amounts of time. If this is really a major concern, then the recommendation would be to limit the current going into the VD pin to under 1mA in order to stay well below the absolute maximum rating.

    So overall, the application circuit of figure 8-1 does seemingly contradict the FAQ guidance to never allow VD to exceed VA by more than 0.3V, but there are also additional considerations that can be accounted to ensure safe operation if the absolute maximum does happen to be violated.

    Regards,
    Joel