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ADC108S102: About the SCLK falling edge of the ADC108S102

Tada Satoshi
Prodigy 10 points
Part Number: ADC108S102

Tool/software:

Our company controller outputs SCLK and inputs it to the ADC108S102.

Refer to FIGURE 2. ADC108S102 Serial Timing Diagram in Datasheet of ADC108S102.
It seems to latch DIN at the rising edge and output DOUT at the falling edge.

However, when the ADC108S102 outputs DOUT, it is not the "rising edge of SCLK received from the controller". Is it the specification that the falling edge timing is created in the ADC108S102 based on the "rising edge" of SCLK from the controller and DOUT is output at that timing?
In other words, is the ADC108S102 side using the falling edge of SCLK for control?

As the background of your question, when we were observing the waveform of our company substrate, we observed a slightly stepped waveform at the falling edge of SCLK.
However, if you don't use the falling edge for control, I thought you don't need to worry about this step, so I asked you this time.

  • 0
    TI__Expert 6990 points

    Hi Satoshi-san,

    To clarify, the ADC108S102 changes data on the DOUT pin on SCLK falling edges, therefore DOUT is valid to be read by the MCU on rising edges. The ADC108S102 reads DIN on the SCLK rising edge, so the MCU should change the data on SCLK falling edges. Both DIN and DOUT are then compatible with SPI mode 3 (CPOL = 1, CPHA = 1).

    The datasheet is written from the perspective of the ADC in a vacuum. Therefore, it changes DOUT on falling edges and will sample the DIN pin on rising edges. Let me know if that makes more sense.

    If the SCLK falling edge is not clean, it will more than likely be okay, but there could be a case where the ADC doesn't detect a falling edge and doesn't transition the data on the DOUT pin. I would not expect there to be any impact in practice however, unless the SCLK does not drop below the digital input low voltage of 0.8V before it tries rising again.

    Regards,
    Joel

  • 0 in reply to Joel Meraz
    Prodigy 10 points

    Thank you for an answer.

    Let me check in more detail.
    Is the input of SCLK a hysteresis buffer?
    If it is hysteresis, once the VIL voltage falls below 0.8 V, I think it will not malfunction unless the VIH voltage exceeds 2.1 V.

    Also, the following waveforms are observed in our company, but will there be a problem with this waveform?
    During the fall of SCLK, a step is observed in the waveform around VIL=0.8 V.

  • 0 in reply to Tada Satoshi
    TI__Expert 6990 points

    Hi Satoshi-san,

    I do believe that the digital inputs to the device, including the SCLK pin, provide some noise immunity. The device should not interpret this slight glitch in the waveform as another rising edge according to the digital logic levels described in the datasheet. 

    Regards,
    Joel