Part Number: DAC38J84EVM
Other Parts Discussed in Thread: LMK04828
Tool/software:
I don't understand the frequency relation in this setup(TI_JESD204_IP_KCU105_DAC38J84_841.zip ) which is the answer in this question.
Why the J17 is fed by a 409.6MHz signal? I see from vivado that there's a pll ip convert a 80MHz to 20MHz which is the sys_clk. And I think this in reality should be 78.125 to 19.53125MHz and that sys_clk can drive a 2.44MHz sine wave shown in the end. But I don't understand how the clock chip convert a external 409.6MHz to 78.125MHz. In the LMK04828 controls clock output setting, the DCLK divider is 32 which I think means the external 409.6 is down convert to 409.6/32 to 12.8MHz.
