Tool/software:
Dear all,
I'm currently evaluating the JESD204C IP core developed by Texas Instruments for Xilinx FPGAs. I followed these steps as per the documentation:
1. Opened my project in Vivado.
2. Set the repository path to the TI JESD204C IP directory as follows:
However, I'm encountering errors when generating the bitstream file.
Error messages
Synthesissynth_1[Designutils 20-2385] This program cannot decrypt an IEEE-1735 envelope without a Xilinx key. ["E:/JESD_Projects/TI_JESD/TI204_LATEST/project_1/project_1.srcs/sources_1/imports/TI204_LATEST/TI_204c_CoreIP/Vivado_2022_and_Newer/rtl/TI_204c_IP_questasim.svp":302]
[Constraints 18-1056] Clock 'fpga_ref_clk' completely overrides clock 'sys_clk_p'.
New: create_clock -period 5.000 -name fpga_ref_clk [get_ports sys_clk_p], ["E:/JESD_Projects/TI_JESD/TI204_LATEST/project_1/project_1.srcs/constrs_1/imports/zc706_8b10b/constraints.xdc": and 2]
Previous: create_clock -period 5.000 [get_ports sys_clk_p], ["e:/JESD_Projects/TI_JESD/TI204_LATEST/project_1/project_1.gen/sources_1/ip/sys_pll/sys_pll/sys_pll_in_context.xdc": and 1]
[Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_pins TI_IP_inst/mgt_rx_usrclk2]]'. ["E:/JESD_Projects/TI_JESD/TI204_LATEST/project_1/project_1.srcs/constrs_1/imports/zc706_8b10b/constraints.xdc":9]
ImplementationDesign Initialization[Designutils 20-1280] Could not find module 'gtx_8b10b_rxtx'. The XDC file e:/JESD_Projects/TI_JESD/TI204_LATEST/project_1/project_1.gen/sources_1/ip/gtx_8b10b_rxtx/gtx_8b10b_rxtx.xdc will not be read for any cell of this module.
[Constraints 18-1055] Clock 'fpga_ref_clk' completely overrides clock 'sys_clk_p', which is referenced by one or more other constraints. Any constraints that refer to the overridden clock will be ignored.
New: create_clock -period 5.000 -name fpga_ref_clk [get_ports sys_clk_p], ["E:/JESD_Projects/TI_JESD/TI204_LATEST/project_1/project_1.srcs/constrs_1/imports/zc706_8b10b/constraints.xdc": and 2]
Previous: create_clock -period 5.000 [get_ports sys_clk_p], ["e:/JESD_Projects/TI_JESD/TI204_LATEST/project_1/project_1.gen/sources_1/ip/sys_pll/sys_pll.xdc": and 56]
[Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_pins TI_IP_inst/mgt_rx_usrclk2]]'. ["E:/JESD_Projects/TI_JESD/TI204_LATEST/project_1/project_1.srcs/constrs_1/imports/zc706_8b10b/constraints.xdc":9]
[Vivado 12-5201] set_clock_groups: cannot set the clock group when only one non-empty group remains. ["E:/JESD_Projects/TI_JESD/TI204_LATEST/project_1/project_1.srcs/constrs_1/imports/zc706_8b10b/constraints.xdc":9]
[Project 1-486] Could not resolve non-primitive black box cell 'TI_204c_IP' instantiated as 'TI_IP_inst' ["E:/JESD_Projects/TI_JESD/TI204_LATEST/project_1/project_1.srcs/sources_1/imports/TI204_LATEST/reference_designs/zc706_8b10b/rtl/TI_204c_IP_ref.sv":520]
Opt DesignDRCNetlistDesign Level[DRC INBB-3] Black Box Instances: Cell 'TI_IP_inst' of type 'TI_204c_IP' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
[Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
I’ve attached images and error logs for reference.
Could anyone assist in troubleshooting this issue? Any advice on how to resolve these errors would be greatly appreciated.
Also, if there’s any known issue with this version of Vivado 2023.1 or a specific configuration that I might be missing, please let me know.
Thanks in advance!
Best regards,
akash
