Tool/software:
Hi All,
There is a bit of problem when trying to add the JESD204C IP core (TI_204c_IP) on the current version of Vivado 2023.1 for the ZC706 board. I've added the IP to my design, but I'm getting the following errors during the implementation phase:DRC. Opt_design not run.
impl_log.txt
*** Running vivado
with args -log TI_204c_IP_ref.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source TI_204c_IP_ref.tcl -notrace
****** Vivado v2023.1 (64-bit)
**** SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
**** IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
**** SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source TI_204c_IP_ref.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/JESD_Projects/TI_JESD/TI_JESD204_IP_Reference_Designs/5-TI_JESD204_IP_Reference_Designs/ZC706_AFE79xx_8b10b_10Gbps/AFE79xx_8b10b_10Gps_ZC706'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.1/data/ip'.
Command: link_design -top TI_204c_IP_ref -part xc7z045ffg900-2
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7z045ffg900-2
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/sys_pll/sys_pll.dcp' for cell 'pll_inst'
INFO: [Project 1-454] Reading design checkpoint 'e:/JESD_Projects/TI_JESD/TI_JESD204_IP_Reference_Designs/5-TI_JESD204_IP_Reference_Designs/ZC706_AFE79xx_8b10b_10Gbps/AFE79xx_8b10b_10Gps_ZC706/Design Files/ip/vio/vio.dcp' for cell 'vio_inst'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_samples/ila_samples.dcp' for cell 'rx_refdesign_gen.refdesign_rx_inst/ila_samples_inst'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/vio_ilas/vio_ilas.dcp' for cell 'rx_refdesign_gen.refdesign_rx_inst/vio_ilas_inst'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_rx_link/ila_rx_link.dcp' for cell 'rx_refdesign_gen.refdesign_rx_inst/ila_link_rx_inst/ila_gen.ila_link_inst'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_tx_link/ila_tx_link.dcp' for cell 'tx_refdesign_gen.refdesign_tx_inst/ila_link_tx_inst/ila_gen.ila_link_inst'
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.254 . Memory (MB): peak = 2575.309 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 903 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Chipscope 16-324] Core: rx_refdesign_gen.refdesign_rx_inst/ila_link_rx_inst/ila_gen.ila_link_inst UUID: 3332439c-ac7b-5e58-84c3-758282f8309b
INFO: [Chipscope 16-324] Core: rx_refdesign_gen.refdesign_rx_inst/ila_samples_inst UUID: b89f6d38-8398-58c9-9642-00a7d7a12c40
INFO: [Chipscope 16-324] Core: rx_refdesign_gen.refdesign_rx_inst/vio_ilas_inst UUID: c81780f7-ea59-52f0-b233-1c96726e8189
INFO: [Chipscope 16-324] Core: tx_refdesign_gen.refdesign_tx_inst/ila_link_tx_inst/ila_gen.ila_link_inst UUID: e9f14dfd-73c5-58a8-a2f7-85749c36223f
INFO: [Chipscope 16-324] Core: vio_inst UUID: 10b64158-46a8-5b75-96e0-7529a8f6e526
Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_rx_link/ila_v6_2/constraints/ila_impl.xdc] for cell 'rx_refdesign_gen.refdesign_rx_inst/ila_link_rx_inst/ila_gen.ila_link_inst/inst'
Finished Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_rx_link/ila_v6_2/constraints/ila_impl.xdc] for cell 'rx_refdesign_gen.refdesign_rx_inst/ila_link_rx_inst/ila_gen.ila_link_inst/inst'
Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_rx_link/ila_v6_2/constraints/ila.xdc] for cell 'rx_refdesign_gen.refdesign_rx_inst/ila_link_rx_inst/ila_gen.ila_link_inst/inst'
Finished Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_rx_link/ila_v6_2/constraints/ila.xdc] for cell 'rx_refdesign_gen.refdesign_rx_inst/ila_link_rx_inst/ila_gen.ila_link_inst/inst'
Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_samples/ila_v6_2/constraints/ila_impl.xdc] for cell 'rx_refdesign_gen.refdesign_rx_inst/ila_samples_inst/inst'
Finished Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_samples/ila_v6_2/constraints/ila_impl.xdc] for cell 'rx_refdesign_gen.refdesign_rx_inst/ila_samples_inst/inst'
Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_samples/ila_v6_2/constraints/ila.xdc] for cell 'rx_refdesign_gen.refdesign_rx_inst/ila_samples_inst/inst'
Finished Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_samples/ila_v6_2/constraints/ila.xdc] for cell 'rx_refdesign_gen.refdesign_rx_inst/ila_samples_inst/inst'
Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_tx_link/ila_v6_2/constraints/ila_impl.xdc] for cell 'tx_refdesign_gen.refdesign_tx_inst/ila_link_tx_inst/ila_gen.ila_link_inst/inst'
Finished Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_tx_link/ila_v6_2/constraints/ila_impl.xdc] for cell 'tx_refdesign_gen.refdesign_tx_inst/ila_link_tx_inst/ila_gen.ila_link_inst/inst'
Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_tx_link/ila_v6_2/constraints/ila.xdc] for cell 'tx_refdesign_gen.refdesign_tx_inst/ila_link_tx_inst/ila_gen.ila_link_inst/inst'
Finished Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/ila_tx_link/ila_v6_2/constraints/ila.xdc] for cell 'tx_refdesign_gen.refdesign_tx_inst/ila_link_tx_inst/ila_gen.ila_link_inst/inst'
Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/sys_pll/sys_pll_board.xdc] for cell 'pll_inst/inst'
Finished Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/sys_pll/sys_pll_board.xdc] for cell 'pll_inst/inst'
Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/sys_pll/sys_pll.xdc] for cell 'pll_inst/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/sys_pll/sys_pll.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/sys_pll/sys_pll.xdc:57]
Finished Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/sys_pll/sys_pll.xdc] for cell 'pll_inst/inst'
Parsing XDC File [e:/JESD_Projects/TI_JESD/TI_JESD204_IP_Reference_Designs/5-TI_JESD204_IP_Reference_Designs/ZC706_AFE79xx_8b10b_10Gbps/AFE79xx_8b10b_10Gps_ZC706/Design Files/ip/vio/vio.xdc] for cell 'vio_inst'
Finished Parsing XDC File [e:/JESD_Projects/TI_JESD/TI_JESD204_IP_Reference_Designs/5-TI_JESD204_IP_Reference_Designs/ZC706_AFE79xx_8b10b_10Gbps/AFE79xx_8b10b_10Gps_ZC706/Design Files/ip/vio/vio.xdc] for cell 'vio_inst'
Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/vio_ilas/vio_ilas.xdc] for cell 'rx_refdesign_gen.refdesign_rx_inst/vio_ilas_inst'
Finished Parsing XDC File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/vio_ilas/vio_ilas.xdc] for cell 'rx_refdesign_gen.refdesign_rx_inst/vio_ilas_inst'
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'gtx_8b10b_rxtx'. The XDC file c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/gtx_8b10b_rxtx/gtx_8b10b_rxtx.xdc will not be read for any cell of this module.
Parsing XDC File [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc]
CRITICAL WARNING: [Constraints 18-1055] Clock 'fpga_ref_clk' completely overrides clock 'sys_clk_p', which is referenced by one or more other constraints. Any constraints that refer to the overridden clock will be ignored.
New: create_clock -period 8.138 -name fpga_ref_clk [get_ports sys_clk_p], [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:2]
Previous: create_clock -period 8.138 [get_ports sys_clk_p], [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/sys_pll/sys_pll.xdc:56]
Resolution: Review the constraint files and remove the redundant clock definition(s). If the clock constraints are not saved in a file, you can first save the constraints to an XDC file and reload the design once the constraints have been corrected.
INFO: [Timing 38-2] Deriving generated clocks [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:8]
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_pins TI_IP_inst/mgt_rx_usrclk2]'. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:9]
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:9]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_pins TI_IP_inst/mgt_rx_usrclk2]]'. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:9]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group '. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:9]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
CRITICAL WARNING: [Vivado 12-5201] set_clock_groups: cannot set the clock group when only one non-empty group remains. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:9]
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_pins TI_IP_inst/mgt_tx_usrclk2]'. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:10]
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:10]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_pins TI_IP_inst/mgt_tx_usrclk2]]'. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:10]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group '. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:10]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
CRITICAL WARNING: [Vivado 12-5201] set_clock_groups: cannot set the clock group when only one non-empty group remains. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:10]
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_pins TI_IP_inst/mgt_rx_usrclk2]'. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:13]
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:13]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_clocks -of_objects [get_pins TI_IP_inst/mgt_rx_usrclk2]]'. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:13]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_pins TI_IP_inst/mgt_rx_usrclk2]'. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:14]
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:14]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-to [get_clocks -of_objects [get_pins TI_IP_inst/mgt_rx_usrclk2]]'. [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc:14]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
Finished Parsing XDC File [C:/Users/user/Downloads/project_8/project_8.srcs/constrs_1/imports/Design Files/constraints.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'TI_204c_IP' instantiated as 'TI_IP_inst' [C:/Users/user/Downloads/project_8/project_8.srcs/sources_1/imports/rtl/TI_204c_IP_ref.sv:520]
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 3384.633 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 176 instances were transformed.
CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 176 instances
28 Infos, 4 Warnings, 11 Critical Warnings and 0 Errors encountered.
link_design completed successfully
INFO: [Common 17-600] The following parameters have non-default value.
tcl.statsThreshold
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z045'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z045'
Parsing TCL File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/gtx_8b10b_rxtx/tcl/v7ht.tcl] from IP C:/Users/user/Downloads/project_8/project_8.srcs/sources_1/ip/gtx_8b10b_rxtx/gtx_8b10b_rxtx.xci
Sourcing Tcl File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/gtx_8b10b_rxtx/tcl/v7ht.tcl]
****************************************************************************************
* WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. *
* Your current part is xc7z045. *
****************************************************************************************
Finished Sourcing Tcl File [c:/Users/user/Downloads/project_8/project_8.gen/sources_1/ip/gtx_8b10b_rxtx/tcl/v7ht.tcl]
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
ERROR: [DRC INBB-3] Black Box Instances: Cell 'TI_IP_inst' of type 'TI_204c_IP' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
INFO: [Project 1-461] DRC finished with 1 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.602 . Memory (MB): peak = 3384.633 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
34 Infos, 4 Warnings, 11 Critical Warnings and 2 Errors encountered.
opt_design failed
INFO: [Common 17-600] The following parameters have non-default value.
tcl.statsThreshold
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
INFO: [Common 17-206] Exiting Vivado at Wed Nov 6 11:48:09 2024...
below is the error
- Synthesis
- synth_1
- [Constraints 18-1056] Clock 'fpga_ref_clk' completely overrides clock 'sys_clk_p'. New: create_clock -period 8.138 -name fpga_ref_clk [get_ports sys_clk_p], ["C:/Users/user/Downloads/project_9/project_9.srcs/constrs_1/imports/DesignFiles/constraints.xdc": and 2] Previous: create_clock -period 8.138 [get_ports sys_clk_p], ["c:/Users/user/Downloads/project_9/project_9.gen/sources_1/ip/sys_pll/sys_pll/sys_pll_in_context.xdc": and 1]
- [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_pins TI_IP_inst/mgt_rx_usrclk2]]'. ["C:/Users/user/Downloads/project_9/project_9.srcs/constrs_1/imports/DesignFiles/constraints.xdc":9]
- Implementation
- Design Initialization
- [Constraints 18-1055] Clock 'fpga_ref_clk' completely overrides clock 'sys_clk_p', which is referenced by one or more other constraints. Any constraints that refer to the overridden clock will be ignored. New: create_clock -period 8.138 -name fpga_ref_clk [get_ports sys_clk_p], ["C:/Users/user/Downloads/project_9/project_9.srcs/constrs_1/imports/DesignFiles/constraints.xdc": and 2] Previous: create_clock -period 8.138 [get_ports sys_clk_p], ["c:/Users/user/Downloads/project_9/project_9.gen/sources_1/ip/sys_pll/sys_pll.xdc": and 56]
- [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_pins TI_IP_inst/mgt_rx_usrclk2]]'. ["C:/Users/user/Downloads/project_9/project_9.srcs/constrs_1/imports/DesignFiles/constraints.xdc":9]
- [Vivado 12-5201] set_clock_groups: cannot set the clock group when only one non-empty group remains. ["C:/Users/user/Downloads/project_9/project_9.srcs/constrs_1/imports/DesignFiles/constraints.xdc":9]
- [Project 1-486] Could not resolve non-primitive black box cell 'TI_204c_IP' instantiated as 'TI_IP_inst' ["C:/Users/user/Downloads/project_9/project_9.srcs/sources_1/imports/rtl/TI_204c_IP_ref.sv":520]
- Opt Design
- DRC
- Netlist
- Design Level
- [DRC INBB-3] Black Box Instances: Cell 'TI_IP_inst' of type 'TI_204c_IP' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
- [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
There is a problem where Vivado doesn’t seem to know the definition of the IP core and is treating it as a black box.
But if you look down it shows that the IP core is included in my project and all the necessary files are derived.
Is anyone else familiar with this problem? Feedback on better ways of solving this would be highly welcome.
Thanks and regards
balu
