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Original question:

TI-JESD204-IP: zcu102_8b10b IP works fine for 8 lanes but gives rx_lane_invalid_eomf_err_count

TI-JESD204-IP: Two ADCs (ADS52J900) to be connected to single JESD Instantiation in FPGA

Trushal Alshi
Prodigy 100 points
Part Number: TI-JESD204-IP

Tool/software:

Hello,

We want to connect two ADC viz ADS52J900 to single JESD instantiation in FPGA. The ADC is to be operated in 4 lane mode. Can we interface the two ADCs to the single  JESD with 8 lanes.. Please ref to block diagram attached. Also please suggest any particular care for Fs (Sampling frequency) clock to ADC. Is it to be sourced from same source e.g.  Clock chip  which is sourcing ref_clk of JESD core. In other words, does Fs clock in of ADCs  need to in phase reference with ref_clk?  Thanks!

 

  • +1
    TI__Intellectual 1720 points

    Hi Trushal,

    Yes, you can connected two 4 lane links (ADCs) to a single JESD IP configured for 8 lanes (with the SYNCn fanned out to both ADCs, as you have done). For this to work, the ADC's will need to be synchronized using SYSREF.

    The Fs and ref_clock do need to be phase aligned because you are generating the SYSREF from the FPGA. Even in that case, it will be difficult to meet timing at the ADC, as you will have a 2ns window. In addition, I am not sure if you need deterministic latency in this application. Overall, it may be best to generate clocks and SYSREF from a common source and feed the outputs to the ADC's and the FPGA.

    Regards,

    Ameet

  • 0 in reply to Ameet Bagwe
    Prodigy 100 points

    Hi Amit,

    Thanks for the clarification and suggestion. Yes we plan to use external ref_clk and sysref source.

    Thanks,

    Trushal