Other Parts Discussed in Thread: ADS52J90
Tool/software:
Hello,
I am not sure if this question to be asked in ADS52J900 specific thread but since related to JESD IP, posting it here.
In 4 lane mode of ADC ADS52J90, (Ref : Table 29. Multiframe Size in Different Modes) mentioned to be 3 ( note mentions: equal to the multiframe size (in frames) minus 1). Little confused about what exact value to be put in jesd_link_params.vh , whether is should be 3 or 4.
So for validation, We modified the parameter RX_K_VAL and TX_K_VAL to "3" in JESD reference design. The simulation works fine but in reality on the board with physical loopback, this does not work. The JESD qpll locks but the TX and RX does not show any transaction in loopback.
However this loopback works fine with RX_K_VAL and X_K_VAL set to "4". Is there any other parameter that needs to be changed. This experiment was done for various Lines rates and ref_clk, sys_clk settings are supposed to be correct. Datawidth is 64 bits.
Thanks,
Trushal
