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DAC38RF84: SYSREF and start-up sequence

Peter Tsoulos
Prodigy 40 points

Part Number: DAC38RF84

Tool/software:

Hello,

I am driving the DAC38RF84 from an FPGA and do not require synchronisation of the DAC with any other devices.

I gather from reading other posts that the SYSREF input signal is required regardless for subclass 1 and the internal SYSREF generator (LCMGEN) should not be used. As such I have a few questions about the use of SYSCLK:

The recommended start-up sequence in the datasheet says "Start SYSREF Generation" following the VCO tuning process. Does this mean enable the external SYSGEN source (rather than set some register field)?

Can I simply use the same external DACCLK source frequency (250 MHz in my case) as the SYSREF source? 

Does the external SYSRF source need to be disabled during start up until after the VCO tuning or can it run continuously?

If it has to be started only after VCO tuning, can I disable SYSREF after the startup sequence is completed, or is it best to keep this signal operating during normal operation? 

Thanks

  • 0
    TI__Mastermind 24200 points

    Hi Peter,

    Yes, the SYSREF source is what is meant by start sysref generation and not to write some register. 250MHz is too high for sysref input. The maximum sysref frequency depends on the specific operating mode and is equal to the following:

    N=LCM(CLKJESD_DIV, 4*K*F).

    For instance, if interpolation = 18, clock=6000MSPS, LMFS=8-4-1-1 with K value of 20. CLKJESD_DIV can be calculated as follows: for 8-4-1-1 x18 interpolation, the CLKJESD_DIV[3:0] = 4b'0111 which corresponds to div32 using Table 7-71.

    This means N = LCM(32, 4*20*1) = LCM(32, 80). Since 80/32 is not an integer, the LCM needs to be calculated. In this case, N = 160 and the max legal sysref frequency for this mode would be 6000MSPS / 160 = 37.5MHz. Any integer divide from this value is possible (18.75MHz, 9.375MHz, ...) 

    The sysref can be enabled in a continuous mode during the full configuration of the DAC, and once the VCO tuning is completed, just ensure there is adequate time delay for ~4 SYSREF periods so the internal blocks can align. After the DAC link is up, you can disable the sysref generator output during runtime to save on power/prevention against spurs.

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 40 points

    Hi Chase,

    Thanks for your response, that's  resolved most of my questions. I do have a couple of follow-on questions relating to SYSREF and sample rates:

    Can I confirm that the sample clock frequency (6000 MSPS in the example above) is the frequency of the samples output from the RF DAC (not the input sample rate over JESD204B)?

    I'm generating data samples at 200 MSPS in my FPGA that I want to send to the RF DAC, so this is my baseband data rate. However, I'll need K = 20 which presumably means that only one frame in the multi-frame conveys any sample data, so the baseband data rate is actually 1/20 of this?

    Assuming the baseband data rate is 200 MSPS, then the SerDes rate is 1.25 x M/L x 200 x 16 = 2 GSPS.

    Thanks,

    Peter

  • +1 in reply to Peter Tsoulos
    TI__Mastermind 24200 points

    Hi Peter,

    The K value is the number of frames which composes a multi-frame. The K dependency for the sysref calculation is to ensure that the sysref frequency is an integer multiple of the multi-frame boundary. The data rate into the DAC being 200MSPS can be called the baseband data rate but is more commonly referred to as input datarate, while the DAC analog samples output is referred to as the output datarate, or the DAC's sample rate. The sample rate will always be the input rate multiplied by the DAC's interpolation factor.

    The samples fed into the DAC will need to be updated each frame or else the DAC will receive an empty FIFO error. For example, in LMFS=8-4-1-1 mode, there are 4 (M=4) converters sending 1 (S=1) sample per frame. This corresponds to 4*(1 sample)*(16 bit/sample) = 64 bits per frame, which you can also think of as the # of 8-bit octets per frame (F=1) is 1, so (8 bits/(1 octet/frame))* 8 lanes (L=8) is 64-bits total throughput per frame. A multi-frame will simply consist of K*(8*F) bits wide.

    The data fed to the DAC should be passed in at the size of the TX lane data width by the JESD IP, commonly 32- or 64-bit wide. So if your lane data width is 32-bit, then your lane composition on the FPGA should account for 4 samples worth of data per lane like below. This input datarate below must be what is 200MSPS, so your TX lane data width sample memory must be updated at the following rate: 200MSPS / 4 (samples/lane width = 32bit) = 50MSPS. Does this help>?

    DA0[15:8], DA1[15:8], DA2[15:8], DA3[15:8]

    DA0[7:0], DA1[7:0], DA2[7:0], DA3[7:0]

    ....

    DD0[15:8], DD1[15:8], DD2[15:8], DD3[15:8]

    DD0[7:0], DD1[7:0], DD2[7:0], DD3[7:0]

    Thanks, Chase