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ADS1258: ADS1258 Register Write command Problem, configuring registers

Part Number: ADS1258


Tool/software:

Hi,

I am working on the ADS1258 and I have questions about the Register Write Command.

First, I am sending a register write command (the first three bits are "011"=Register Write Command) in order to configure the SINGLE-ENDED inputs I want to be active (the address in the Command Byte I am sending is "0100" making register MUXSG0 ="00000001"... which means I want Channel AIN0 to be active), this having the Multiple Register Access MUL='0' which means I want to configure only that AIN, so I am sending as Command "01100100", and as Register Data "00000001"

Then, keeping the Multiple Register Access MUL='0', I want to configure AIN8 as active, so I am sending as Command "01100101" (address for register MUXSG1) and as Register Data "00000001", and one of the following occurs

     - It is configured correctly, with AIN0 and AIN8 active

     - The MUXSG1 register is configured incorrectly, leaving all the AINs in this register (AIN8 to AIN15) as active, MUXSG1 = "11111111"

Analyzing this problem, I have reached the part of the communication with the ADC by SPI, and I understand that the same SPI bus is used for the communication to configure the ADC and to read the converted data... and I have seen that I am trying to configure it when the converted data is being communicated by the SPI
My question is: Is there a time rule in which I must wait after the SPI is being used as a communication for converted data to use it later as a configuration communication? or vice versa, wait after a configuration to read the converted data?

It seems to me that my problem is on this side, since sometimes it is configured correctly and other times it is not.

  • For update
    I set START as low when configuring (sending Register Write Command), in order to prevent the ADC from converting data while I'm configuring it
    And I have another question, for how long does DRDY stays LOW when I don't send sclk (SPI clock) which means I am not reading converted data?
  • Hi Juan B

    It will be helpful to see the data communication, instead of just describing it. That is the only way we can verify the communication is correct, both the commands you are sending to and receiving from the ADC, as well as the timing

    Can you provide logic analyzer plots showing all digital signals (CS, SCLK, DOUT, DIN, DRDY) during the data transactions?

    -Bryan

  • Hi Bryan,

    In the attached image I show the signals that are being used in both, reading converted data and configuring the ADC

    First in the image "IMAGE 1", the reading of converted data occurs, and in this case right after this a new configuration to the ADC, here I am sending a command to modify the MUXSG1 register (address "0101") wanting to have AIN8 and AIN15 active... but here this register configured as "11111111" making this 8 AINs active (AIN8 to AIN15)

  • Hi Juan B

    What is going on in the circled image below? You say that you are "reading data", so why are sending 5x8 = 40 SCLKs?

    Also, if you are going to read data using Channel Data Read Direct, you must toggle CS once the data read is complete. This looks like what you are doing since you don't have any activity on DIN

    -Bryan

  • Hi Bryan

    I am sending 40 SCLKs so that at the end I have the signal back to "zeros", with the objective that at the next data reading I can see the MISO signal starting at "zeros"

    And, in the attached image you can see how CS goes HIGH but for a very short time, because it immediately goes back to LOW to now use the SPI to configure the ADC, "configuring"

    For update, when I want to configure the ADC, I set the conversion START signal to LOW and wait for the last DRDY that is in progress

  • Hi Juan B,

    What SCLK and CLK frequencies are you using?

    -Bryan

  • Hi

    CLK = 16 MHz

    SCLK = 10 MHz

    For update, I realize that the ADC is configured wrong because I am using the Auto-Scan mode where I see that having 1 channel active the ADC sampling frequency is 23.739 kHz, and when I try to configure it as I want it and when it is configured wrong I get less sampled points in the same signal, so I conclude that the sampling frequency changed and I conclude that it is because more channels were activated for conversion.

  • Hi Juan B,

    Thanks for providing this info. You need to review the timing info in the ADS1258 datasheet, see below

    The SCLK speed must be <1/2 of CLK. And the CS period must follow the same restriction. The CS pulse you are showing in one of your previous images is definitely less than the SCLK period, which is already too short

    -Bryan

  • Hi Bryan

    I realize that I did not take into account these restrictions... I will try to apply them and analyze the operation.
    Thank you very much, according to the results I will ask again.

    On the other hand, taking advantage of the open forum space, is there any way to know how a specific register is configured... for example I configure the MUXSG0 register as “10000001”, I want to see that configuration so I guess I should send a command for this with the register address, hoping that what I get back is that “10000001”... I am not sure if it is the Register Read Command = “010” having as Command “01000100”

  • Hi Juan B

    Please refer to Table 14 in the ADS1258 datasheet for instructions about commands, specifically the "Register Read Command"

    Also, can you please start a new thread if your questions are unrelated to the original topic? This way if anyone has a similar question in the future they will be able to find it easier

    -Bryan

  • Hi Bryan

    Thanks for replying, I have started a new thread for the other question, sorry for asking it in this thread

    Talking about the question in this thread... I changed the SCLK clock frequency to 1 MHz, and I can corroborate that indeed the clock is at that frequency, but when I send a new configuration command the ADC is not configured as I expect... moreover, the data that is sent from the ADC by the MISO pin are not according to what I configure and even receive in the STATUS BYTE in table 12. I get in the CHID bits values that are not found in table 13. for example 1Eh.
    I don't know if the frequency is now too low, or other restrictions are not met

    In the attached image, you can see how the first values that I receive in the MISO signal (STATUS BYTE) are “11111110”, making the CHID “11110” (1Eh), which is not what was configured.

  • Hi Juan B,

    Did you also change the CS timing, as discussed in the last post?

    Also, what are your register settings? Can you read them back from the ADC so we know exactly how the device is configured (instead of what you sent to the ADC, because it is possible whatever you sent did not get written correctly)

    FYI it is a holiday here in the US, please do not expect additional responses until next week

    -Bryan

  • Hi Bryan 

    I'm sorry for the time I took to answer, I was doing tests taking into account what you told me and analyzing what I was getting.
    The problem was with the SPI clock frequency, I organized it and also organized the other signals so that everything complied with the restrictions; so now it is working correctly and I can configure the registers I want with the values I want and it does not get out of configuration as before.

    Thank you very much for everything

  • Hi Juan B,

    I am glad this was resolved!

    -Bryan