Tool/software:
AFE5818
ADC PATTERN GENERATION: 6 ADCs 96 channels, sampling frequency: 19.2 msps
Ramp pattern generation using Register 2 of ADC
Sine wave pattern generation after feeding 200 Khz 200mVpp
ADC Resolution: 14 bits
Data format: Signed decimal
We are configuring the ADC by setting the value 0x020000 into the register, but we are noticing that the resulting pattern in the ILA does not generate a sine wave in signed decimal format. In contrast, when using other modes of operation, the pattern generation works as expected, and we observe the ramp pattern functioning correctly.
Are we plotting the data in the correct format? Is there any additional configuration that needs to be done?
All the patterns when generated from FPGA are getting generated and we are able to see in the ILA but when we are feeding a signal from external source to the ADC(AFE5818) we are not seeing the right waveform which we should so please suggest if there is anything that we can address both from the Hardware side and any register configurations
