Other Parts Discussed in Thread: DAC39RF10
Tool/software:
Hello,
We are testing DAC39RF10 IC and we would need to know if the following configuration is possible:
- 1 -> PRBS generator inside one FPGA (generating PRBS31 data)
- 2 -> PRBS generator directly attacking only one GTH transceiver (on UltraScale FPGA). So only one lane of the DAC is used.
- 3 -> Encoding 8B/10B is used (configured inside the transceiver)
- 4 -> JTEST register is set to 0x4 (PRBS31 encoding)
- 5 -> Data is not encapsulated in JESD204 protocol. This means that no JESD204 protocol is used. This is the main doubt we have about our setup. We directly attack GTH transceivers with PRBS generator and 8b/10b encoding. So data received by the DAC is not encapsulated on JESD204 .
- 6 -> Activate BER_EN to check errors during communication
We have done several tests and through the GUI for the DAC, we see that BER error counters goes to 0xFF instantly after enable JESD_EN bit on corresponding register.
Does the DAC require data received to be encapsulated on JESD204 protocol?? If not, Do we have to use all lanes (16) to work with JMODE0 , even when JTEST mode is set to 0x04 (PRBS31)??
Thanks by advance!
Regards
