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Original question:

AFE58JD28: Synchronizing two AFE58JD28 AFEs

AFE58JD48: how to use TX_TRIG with AFE58jd48

Gaofeng Zhao
Prodigy 80 points
Part Number: AFE58JD48
Other Parts Discussed in Thread: AFE58JD28, LMK00308, TX08D

Tool/software:

Hi DC team,

I'm confused about how to use TX_TRIG with AFE58jd48, my question is related to this link: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1347004/afe58jd28-synchronizing-two-afe58jd28-afes/5142536?tisearch=e2e-sitesearch&keymatch=afe%20tx_trig#5142536

  • can SYSREF reset the demod and test pattern of AFE58JD48 like TX_TRIG? which is same as AFE58JD28.
  • how should I supply TX_TRIG to several AFE58jd48 to be synchronized ? if I want to synchronize all the TX_TRIG and meet the timing requirements of the system clock, do I have to use a clock buffer, like providing TR_BF_SYNC to the transmitter chip with LMK00308?
  • How to use the clock buffer chip to output the AFE's system clock and TX_TRIG at the same time

  • +1
    TI__Expert 4681 points

    Hi,

    Please see below response:

    • can SYSREF reset the demod and test pattern of AFE58JD48 like TX_TRIG? which is same as AFE58JD28.
      • By default SYSREF wont reset the demod.
    • how should I supply TX_TRIG to several AFE58jd48 to be synchronized ? if I want to synchronize all the TX_TRIG and meet the timing requirements of the system clock, do I have to use a clock buffer, like providing TR_BF_SYNC to the transmitter chip with LMK00308?
      • TX_TRIG will reset the ramp test pattern. So you can enable ramp and apply TX_TRIG and look for ramp data in FPGA to sync channels and devices. Other way is if you are planning to use demod then you can look for SYNC word to align data. You dont need buffer like LMK. TX_TRIG would be coming from FPGA so you can adjust the timing in FPGA to meet the TX_TRIG timing but you still have to route the TX_TRIG length matched across devices.
    • How to use the clock buffer chip to output the AFE's system clock and TX_TRIG at the same time
      • As mentioned above, TX_TRIG shall come from FPGA and by adjusting timing in FPGA, you can meet the target timing between TX_TRIG and ADC clock.

    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    Prodigy 80 points

    Hi Shabbir

    Thanks a lot!  this solved most of my confusion, but here comes two other point:

    • Does adjusting timing of TX_TRIG in FPGA mean I must split one ADC clock to FPGA?
    • what does "Use the same fanout buffer for BF_CLK clock signal to match timing" (in TX08D Datasheet) mean? The LMK00832 should not be able to output two different signals at the same time and adjust their phase. Should the timing of TX_BF_SYNC be adjusted in the FPGA as well？

    Best,

    Gaofeng

  • 0 in reply to Gaofeng Zhao
    TI__Expert 4681 points

    Hi,

    - First of all it will be better to use same ADC_CLK frequency to launch TX_TRIG. So better to route it to FPGA and use it for generating TX_TRIG. You can adjust the output buffer delay min/max limit in timing contraint in FPGA to adjust the TX_TRIG timing if required.

    - Story is differnt for Tx devices. In Tx device, first of all clock frequency is 2x or 4x higher than Rx device. Therefore available timing margin is lower so we have made TR_BF_SYNC also differential and recommend it to route through same buffer for better timing. But in case of Rx, TX_TRIG is single ended so it cant be passed through same buffer. It can come from FPGA and since more time is available therefore it will be ok.

    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    Prodigy 80 points

    Hi Shabbir

    Is it okay to design a system like this?

  • 0 in reply to Gaofeng Zhao
    TI__Expert 4681 points

    Hi,

    Since these parts come under NDA, let us discuss it over mail. Please drop me message on below mail id:

    support_us_afe_tx@list.ti.com 

    Regards,

    Shabbir