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ADC32RF45: JESD204B link error when SYSREF is input

Seiya Toyoda
Prodigy 20 points
Part Number: ADC32RF45
Other Parts Discussed in Thread: LMK04828,

Tool/software:

I am using ADC32RF45 with JESD204B subclass 1 and I/F with FPGA. When I input one pulse of SYSERF from PLL to FPGA and ADC for linking, a disparity error is detected on FPGA side and I cannot link properly.Any suggestions for a solution to this problem would be appreciated.

As a precondition, we would like to make sure that the sample position from which the ADC data is acquired does not shift even if the JESD link is redone by turning the power on and off again. 

Environment:

* Use LMK04828 for PLL

* Use XILINX JESD204 v7.2 IP on FPGA

* Input 3GHz clock to CLKIN1 of LMK04828

Remarks:

* The same phenomenon occurs on evaluation board (ADC32RF45EVM)

* If SYSREF_MUX of LMK04828 is not changed to Normal SYNC but left as SYSREF continuous, it links normally after several SYSREFs.


Attached file contents:

1.  configuration file of PLL used on the evaluation boardLMK04828.cfg
2. configuration file of ADC used on the evaluation boardADC32RF45.cfg

  • 0
    TI__Mastermind 22620 points

    Hi Seiya,

    It seems like only one sysref is being pulsed? The device requires multiple sysref pulses which explains why the link is ok when the LMK is placed into continuous sysref mode and not when in single shot sysref mode. See figure 71 below.

    My advice is to always use continuous sysref and after the link is successful, disable the sysref clock output group on the LMK register setting. This seems like it will fix your issues as you have no issue when using continuous sysref mode.

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 20 points

    Hi Chase,
    Thanks for your quick reply.

    In our design, we use CONTINUOUS SYSREF until the ADC is set up.
    Once the ADC is set up, MASK CLKDIV SYSREF is set to change from CONTINUOUS SYSREF to normal SYNC. During this time the FPGA is in reset. (For more information on the settings, see the attachment to the first question).
    This is because we want to start the link at any timing in the FPGA, not at the timing caused by the frequency divider in the PLL.
    I also want to ensure that when I reboot the system, if I input SYSREF at the same timing, the converted data will be output at the same phase (although there may be a blip of a few clocks). Is this possible?

    Thanks, Seiya