• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 46 subscribers
  • Views 256 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS8688: Unable to configure the desired resolution for All Channels

CJ Mirafuentes
Prodigy 10 points
Part Number: ADS8688


Tool/software:

Hi TI Support Team,


I am encountering an issue while configuring the input range and resolution for the ADS8688. Specifically, the device does not appear to apply the new configuration settings correctly and the response is consistent across all channels (CH0 to CH7). Below are the details of the problem:

  1. Goal:
    I am attempting to set the Range Select Register for all channels to 0101, which corresponds to an input range of 0 to 2.5 x VREF.

  2. Issue:

    • After writing the new input range setting to the Range Select Register for any channel, the register does not reflect the updated value. When I read back the register, it consistently returns 0x00.
    • To confirm this issue, I read the ADC values for all channels with ~0V input, and they return 0x7FFF instead of a value close to zero.
    • This behavior is observed across all channels (CH0 to CH7).

  3. Waveform Confirmation:
    I have verified the SPI communication using a logic analyzer and the waveform for writing the new resolution and range settings matches the protocol in the datasheet. But the Range Select Register remains the same.

  4. Steps Taken for Debugging:

    • Verified SPI timing and communication integrity.
    • Attempted to write to the Range Select Register for all channels individually and in sequence, with the same result.
    • Repeatedly read back the registers after configuration attempts to confirm the behavior.

  5. Questions:

    • Are there specific initialization steps required before configuring the Range Select Register?
    • Is there a required write sequence or delay that I may be missing?
    • Could there be a device-level lock or protection that prevents writing to the Range Select Registers?
    • Is there a common issue that could explain why all channels behave identically and fail to update?

Any insights on this issue would be greatly appreciated, as I am unable to proceed with testing due to the configuration failure.


  • 0
    TI__Guru**** 181511 points

    Hi CJ,

    Welcome to our e2e forum!  While we look over the details you describe above, can you tell us what the logic capture snippet above represents?  Are the SDO and SDI labels swapped by chance?  Can you provide another capture that shows the chip select input along with SDI and SDO?

  • 0 in reply to Tom Hendrick
    Prodigy 10 points

    Hello Tom,

    Yes, the labels were swapped.

    In my hardware setup, the MCU SPI lines are connected to an isolator. The waveform I posted earlier shows the signal directly from the MCU, while the waveform below is the signal after passing through the isolator.

    CH1 - CS 

    • When this signal is HIGH, the  ADS8688 CS pin is Low
    • When this signal is LOW, the  ADS8688 CS pin is High

    CH2 - SCLK: Serial Clock. 
    CH3 - MISO: Master In, Slave Out.
    CH4 - MOSI: Master Out, Slave In.

  • +1 in reply to CJ Mirafuentes
    TI__Guru**** 181511 points

    OK - thanks!

    So your transaction is setting CH6 (0x0B) to the 0-2.5V range (0x05) - can you change the phase relationship of you MOSI so that data is valid on the falling SCLK edge?