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AFE4404: Minimum LEDs duty cycle and time to sampling

Part Number: AFE4404


Tool/software:

Dear Sirs.

I use AFE4404 in low power device. I need to reduce power consumption of LEDs.

Pulse repetition factor is 10ms

Today I switch LED on for 230us and wait 70us between switching the LED On and starting sampling.

It works properly but power consumption is too high.

What is a minimum time that I can switch LEDs ON?

What is a minimum time between switching the LED on and starting sampling? Capacity of photodiode less than 40 pF

Table 7 in datasheet is not clear.

Please advice.

  • Hi Michael,

    Thank you for your post.

    Theoretically, the minimum LED pulse duration would be one CLK_TE period, but this would likely be impractical for your application. CLK_TE is the Timing Engine clock reference, which is equal to the ADC clock divided by the CLKDIV_PRF setting.

    The minimum time between the LED turning on and the start of sampling is defined as t1 in Table 7. This minimum time is typically 20% of the LED on time, but cannot be any less than 25 µs. For low-power applications, we generally recommend starting with an LED pulse duration of 50-100 µs and using a higher TIA gain setting.

    Regards,

    Ryan

  • Thank you for fast response.

    But I am still confused about sampling process.

    How does sampling work? As I see in block diagram Figure 23, sample time charge capacitor CSAMPx. If sample time is enough to charge this capacitor, sampling time more than this shall not affect of DC value. What is a time that enough to charge it to for example 99%?

    Example:

    Assume sampling time is 200 us the same LEDs, LEDs currents,  photodiode and the same optical; pass.

    Assume I get from ADC DC signal 500000 ADC units.

    What will happen with signal if I only change sample time? For example reduce sample time from 200 us to 100 us?

    Will I get from ADC the same 500000 or something else?

    Please advise.

  • Hi Michael,

    The settling time of the sample capacitor is dependent on the bandwidth of the TIA. This is set by choosing the feedback capacitor, CF, in parallel with the gain resistor, RF. If the TIA bandwidth and LED sampling time are enough for the acquired voltage to fully settle across the sampling capacitor, you likely will not notice much difference in the acquired ADC values if the LED sample time is reduced from 200 to 100 µs.

    Once the sampling phase ends, the CSAMPx capacitor is connected to the common CBUF capacitor, where it is driven into the internal sample-and-hold circuit of the ADC. The CBUF cap is shorted across in between conversions in order to minimize crosstalk from the other CSAMPx capacitors.

    Regards,

    Ryan

  • Cf always 5 pF. Rf default 25KOhm, but may be  changed in range from 10KOhm to 100KOhm in my application.

    How can I know minimum sample time that I need in this case?

    Thank you

  • Hi Michael,

    The data sheet recommends setting the TIA time constant to 1/5 or less of the LED sampling duration. Therefore, assuming 100kΩ and 5pF for the TIA, the time constant would be 500 ns. The minimum LED sampling pulse would then be at least 2.5 µs. 

    Regards,

    Ryan

  • Thank you very much. I set 25 us between LED on and starting sample and sampling time 5 us to be on the safe side. It works fine.

    The next my question if my photodiode's capacity is about 80 pF (0 reverse voltage) can I reduce time between switching the LED on and starting sampling less than 25 us? According to datasheet I know that it is not recommended. But does it depend of photodiode capacitance?

     Best regards

    Michael

  • Hi Michael - please excuse the delay as I'm just returning to office from paternity leave.

    I found a note in the Revision History (pg. 2) as well as in the Applications Section (pg. 70) which explains that at least 25µs is recommended to improve ambient light rejection. So it looks like the device will work for t1 < 25µs, but you may find the ambient noise degrades the overall performance.

    Regards,

    Ryan