Tool/software:
Ran into a strange issue when configuring ADS131A04 data converters in chained mode and I though this would be worth sharing.
My configuration:
Two ADS131A04 ADCs sharing the same SPI_CLK, MISO, MOSI, DRDY lines.
First ADS131A04 configured with M0 set to IOVDD, Asynchronous interrupt mode. M1 and M2 tied to ground.
Second ADS131A04 configured with M0 floating, synchronous slave mode. CS wired to DONE line of the first ADC. M1 and M2 tied to ground.
I have a function generator running at 16MHz providing a common clock input line (pin 25) to both parts for testing. This clock signal is always on as it will be in the eventual design.
Configuration of all registers is working correctly. I'm able to write and read every register correctly. I'm using 24 bit mode so my MCU master is sending 6-byte packets via SPI. After the first 3 bytes are sent, the first ADC pulls the DONE line low to select the second ADC. This is all working just as the datasheet says. I'm using the parts in dynamic frame mode without any CRC or hamming.
The instant I write to the ADC_ENA register, the data packet size changes. Through trial and error, I discovered that I have to supply NULL bytes for every channel enabled in the first ADC. If I enable all 4 channels, this means 12 NULL bytes before I send the command to enable the second ADC. The same goes for the subsequent WAKEUP and LOCK commands. From the programming sides, the outgoing WRITE REGISTER commands are different once you enable channels on the first ADC.
Is this described anywhere in the datasheet or in an addendum? This is a very unusual feature or aspect of operating that deserves a callout.
rgds,
Gary
