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ADC12J1600: ADC12QJ1600

Part Number: ADC12J1600
Other Parts Discussed in Thread: ADC12QJ1600

Tool/software:

Hello,

Just down loaded the new version  of  TI204C-IP-Release-v1.12-LATEST (from June 2024).

Does this version is support the ADC12QJ1600 working in JMODE 8  at 1Ghz clock rate  connected to ZU19EG?

Regards,

Giora

  • Hi Giora,

    The TI JESD IP supports all LMFS modes of all TI data converters as it is compliant with the JESD204b/c protocols. These are the steps that you will need to follow:


    1> Start with the ZCU102 loopback reference design. Carry out a complete bitfile generation to ensure that your tool version is compatible with the design. Please keep this project open for reference.

    2> Create a new project with the ZU19EG part (with the same source files)

    2> Edit the jesd parameters (.vh) file to match the JMODE and lane map/polarity settings for the new FPGA

    3> Edit the transceiver to set the lane rate, reference clock, active channels, etc as per the JMODE

    You should now be able to build the design for the ZU19EG FPGA.

    Regards,

    Ameet

  • Hello Ameet,

    Thanks. 

    We do not have the ZCU102 board, instead we have the IWAVE SOM and carrier boards:

    ( iW-RainboW-G35M® )

    So we have to start from bolt 2 of your answer.
    Regards,
    Giora