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ADS131M04-Q1: Help Needed: Basic Communication Between ADS131M04 and RP2040

KIRYOUNG YANG
Prodigy 10 points
Part Number: ADS131M04-Q1
Other Parts Discussed in Thread: ADS131M04,

Tool/software:

Hello,

I am currently working on connecting a Raspberry Pi Pico with the ADS131M04. However, I have encountered some issues.

When I send a basic reset command, there is no response,

and when a register read command is sent, I receive responses that are structurally incorrect.

Below is the pin connection diagram for your reference.

As additional information, all AIN pins are connected to DVDD and DGND.

For the clock setup:

  • CLKIN is configured at 8.196 MHz using the PWM output provided by the RP2040.
  • SCLK is set to 20 MHz.

The voltage supply line (3.3V) fluctuates between 3.26V and 3.22V. The ground line (GND) varies between 0 and 0.025V.

Could you please advise if I am missing something or if there’s anything else I should check?

Thank you for your assistance.

  • 0
    TI__Mastermind 40895 points

    Hi KIRYOUNG YANG,

    Welcome to the TI E2E community! 

    I'm not sure if you have designed and are testing your own circuit board with ADS131M04-Q1 ADC. From your block diagram, you are connecting CAP pin to the GND(AGND), the CAP pin of ADS131M04-Q1 is an analog output pin and a 220nF capacitor should be placed between this pin and the GND. Also, you are placing a 220nF capacitor between DGND and AGND, the DGND should be tied to AGND on the ADS131M04-Q1 ADC. I would recommend you to check all the details in the ADC data sheet.

    By default, the word length of the SPI is 24-bit on ADS131M04-Q1 ADC, so any data/SCLKs that are sent to the ADC should have 24-bit length. Below are timing examples:

     RREG to read the GAIN register (0x4 address):

     

    WREG CLOCK register(0x03) + register data:

    Normal Operation_6 words (24-bit length for each word) in a frame:

    BR,

    Dale

  • 0 in reply to Dale Li
    Prodigy 10 points

    I realized I had incorrectly represented the block diagram. It is configured as you mentioned.


    Currently, I have set SPI CPOL to 0 and SPI CPHA to 1, and it is working correctly.
    However, I have encountered a new issue. I tried changing the WLENGTH in the MODE register to 16-bit, but the intended setting is not being applied.

    The CLOCK and GAIN register writes are working fine.
    Is there anything else I should be aware of?

  • 0 in reply to KIRYOUNG YANG
    TI__Mastermind 40895 points

    Hi KIRYOUNG YANG,

    Can you clarify "the intended setting is not being applied" and also the procedure of your setting?

    BR,

    Dale

  • 0 in reply to Dale Li
    Prodigy 10 points

    Below is the register write

    this is the register read

    The RESERVED parts in the response are also filled with 1s.

  • 0 in reply to KIRYOUNG YANG
    TI__Mastermind 40895 points

    Hi KIRYOUNG YANG,

    Do you mean you could not correctly read the data from the register you wrote previously? Are you able to read the default value of the registers? I saw your /CS is always low from those images, did you toggle the /CS before and after sending the SCLKs to the ADC?

    BR,

    Dale

  • 0 in reply to Dale Li
    Prodigy 10 points

    I apologize for the delayed response.

    I have confirmed that the CS is toggling correctly, and the default values of the registers are being read properly. For example, the STATUS Register responds with 0x0500, and the MODE Register responds with 0x0510.

    However, even after modifying the MODE Register through a write operation, it continues to read back the default value of 0x0510. That said, since the default settings already meet the desired specifications, I have decided to set this issue aside for now and proceeded with voltage measurement testing.

    Unfortunately, I encountered another unexpected issue during the testing. Channels 1 and 2 share the same negative analog input. The problem arises when I change the positive input value of Channel 2, as this also causes the value of Channel 1 to change.

    Could you please advise on how to ensure that each channel operates independently? I would greatly appreciate your guidance on this matter.

    Thank you very much for your support.

  • 0 in reply to KIRYOUNG YANG
    TI__Mastermind 40895 points

    Hi KIRYOUNG YANG,

    Can you clarify "Channels 1 and 2 share the same negative analog input"? Did you just short AIN1N and AIN2N together or short them together then connect them to a signal source? It would be good if you can draw the connections with signal on those pins.

    BR,

    Dale

  • 0 in reply to Dale Li
    Prodigy 10 points

    It turned out that the issue was with my regulator circuit. Everything is working fine now.

    I have one last question.
    When I read data with the default settings, the values are read at intervals of about 500ms.
    When I use Global-Chop Mode, the interval increases to about 1.6 seconds.
    Even if I set the OSR to 64, the values are read at intervals of 67ms.

    This interval is much longer than I expected.
    Is this the expected behavior?
    I would like to know the typical speed under normal conditions.

  • 0 in reply to KIRYOUNG YANG
    TI__Mastermind 40895 points

    Hi KIRYOUNG YANG,

    If your external clock to the ADC is 8.192MHz, the default data rate is 4-ksps with the default 1024 OSR. Please double check and let me know whether your interval of the /DRDY signal is 250us or not.

    BR,

    Dale