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ADC14155 Timing

Dave Altum
Prodigy 10 points

The data sheet provides typical timing of CLK to DAT = 2.0 ns.  I must do a worst case analysis and need the best case and worst case timing of CLK to DATA and CLK to DRDY.  Is this data available?  If not can it be bounded?

 

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    TI__Expert 4340 points

    The 2.0ns value is a measured typical value, but unfortunately limit information for this parameter is not available. I spoke with the designer and he suggested a +/-30% variation (of the 2.0ns delay) across temp/part/board, etc. This is given only as a guideline, not a hard limit number.