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ADS1278-SP: resistors at the ADC input stage

Other Parts Discussed in Thread: ADS1278-SP, ADS1278, OPA2333, LMP2012QML-SP

Hi there,

we are planning to use the ADS1278-SP in High-Resolution with flck=20MHz so fmod=5MHz (Tsample=200ns). With reference to Figure 63-64 on page 30 of the datasheet (SBAS937B, Dec 2018): The datasheet says the sampling capacitor is charged and then discharged and gives the waveforms of S1/S2 (the resistance of the switches or the dead time is not shown).

With this ADC front end, do I have to calculate the maximum input resistors to make sure the sampling capacitor is charged down to 1 LSB in half tsample? Or that is not needed because the circuit shown is too simplified and this requirement is not needed (Figure 65 seems to suggest that?).

Is there a rule to select the input resistance (or is it just driven by the cutoff frequency of the input filter)? I can see on the dev board from TI the resistors are 49R. But our driver opamp OPA2333a gas a pretty weak output current capability (i.e. <5mA) compared to the dev board.

Any further insight would be greatly appreciated!!

Thanks

  • Hello Aieie,

    With a delta-sigma front-end, you have the option to use a relatively large input capacitor, which results in an approximate constant input resistance.  In this case, with the values used in the datasheet, you do not need to settle to 1LSB for each input sample.  You could design an input to fully settle, but then you would need an input amplifier with 100's of MHz of bandwidth to settle within the short sampling times of the input stage.

    However, the input is not an exact linear resistance, and the input amplifier still needs to have a reasonable bandwidth for good operation.  Unfortunately, the OPA2333 is much too low bandwidth (and too high output impedance) for good performance with an fmod=5MHz.  The below guidelines are a good rule of thumb when choosing the input amplifier RC values.  (Cin for the ADS1278 is 9pF)

    I assume you need a Space grade version of the ADS1278 with full radiation specifications?  If so, then I also assume you need similar specifications for the input amplifier.  The LMP2012QML-SP is a better option than OPA2333, offering higher bandwidth along with radiation specifications.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Hi Keith,

    thanks for your prompt reply.

    Ok great thanks for clarifying that I don't need to settle to within 1LSB for each input sample. So I would expect most of the Csample charge comes from the input capacitance (Cdiff in your picture, let's say 2.2nF as per datasheet which is >200 times Csample) and the drive opamp will take care of the average current to keep it topped up (which for fmod=5MHz is <1mA even for the Vref channel).

    To be honest I'm not quite sure why the opamp bandwidth is linked to fmod frequency and not to the actual input signal frequency, can you clarify?
    If we assume a very slow input signal (<1kHz) then the Cdiff voltage can be easily tracked by the OPA2333 and the average current needed is <1mA.

    Would you agree the OPA2333 is ok if the input signal is <1kHz in bandwidth?  

    Regards

  • Hello Aieie,

    I will follow-up with your questions and some recommendations tomorrow.

    Thanks!

    Regards,
    Keith

  • Hello Aieie,

    The input capacitor does supply the majority of the charge for the input sampling capacitor, but it does not supply 100%, which is why the bandwidth of the input amplifier still needs to respond to the modulator frequency.  However, these are general guidelines to achieve best AC and DC performance.  In your case, since the maximum input frequency is 1kHz, you can use a larger input capacitor to further reduce the bandwidth requirements of the input amplifier.

    The below is a suggested circuit if you would like to use the OPA2333 to drive the ADC inputs.  This circuit should work well for 'DC' signals, but will not provide the best AC performance.  The dual-feedback approach will correct for DC errors and improve DC linearity, but AC linearity (THD) will not be optimal.  Also, the below circuit topology will allow you to test different amplifiers if the OPA2333 does not provide the expected performance.

    Regards,
    Keith

  • Hi Keith,

    thanks for your reply and providing a recommendation.
    I think boosting up Cdiff reservoir is a very good idea, after all I can afford the lower input filter cut off frequency. In the dev board schematic I can see a similar approach was followed for Vref (slow response).

    One more question if I may, but it's a bit off topic (I can post it on a new thread if needed):
    I can see that in this thread '[FAQ] ADS1278-SP: Power on / off (up / down) sequencing requirements' your colleague Collin Wells essentially says that the rails power on sequence can be ignored as long as we assert /SYNC after power-up (also the dev board for this part don't sequence the rails).
    That technique will significantly simply the design (it's much easier/cheaper to gate a signal rather than sequencing the rails..). 
    Is this confirmed? Can this note be added into an annex or something?
    Because this part is for high reliability products and I need some sort of official manufacturer statement that it is ok. Do agree?

    Thanks very much for your help!

  • Hello Aieie,

    The power-up sequence requirements are necessary for the internal power-up reset circuit to function correctly.  Asserting the /SYNC pin after the power supplies have stabilized to nominal levels (High->Low->High, tSYN >=1 CLK period) will force a similar reset. 

    Yes, you can ignore the power-up sequence as long as the /SYNC pin is used as described.  The only power-up requirements are then meeting the ABS Max specs during power-up, ensuring no inputs exceed the power supply values during ramp-up by more than +/-0.3V.

    I do not think we will be able to update any official documentation.

    Regards,
    Keith