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ADS1258-EP: Using DMA with ADS1258

Greg Baghdikian
Prodigy 130 points
Part Number: ADS1258-EP
Other Parts Discussed in Thread: ADS1258

Tool/software:

Hi,

We are planning on using 2x ADS1258 on one SPI bus connected to a MCU host that has a DMA engine (SAMv71).

I'd like to transfer samples from the ADS1258s with as little CPU intervention as possible, so I'm looking for ways to transfer all channels' data in "one go", at 10kHz for example.

Reading through the datasheet, it seems like the DRDY line asserts low when new data is ready, and it only holds one samples' worth of data before it gets overwritten.

It sounds like the only intended way to get data off of the ADS1258 is to run an ISR on falling edge of DRDY to transfer one channel at a time, which at high speeds, sounds like a lot of CPU overhead (using DMA for one sample transfers is not worth the overhead).

Is it possible assert the START pin, wait for falling DRDY edge to initiate DMA transfer, and set the SPI clock speed at just the right frequency so that all channel data is valid, deassert START, then wait until the next desired sampling period?

Thanks,

-Greg

  • 0
    TI__Mastermind 47091 points

    Hi Greg Baghdikian,

    Greg Baghdikian said:
    It sounds like the only intended way to get data off of the ADS1258 is to run an ISR on falling edge of DRDY to transfer one channel at a time,

    This is correct. There is no way to get data from more than one channel at a time. If you wait >1 sample period, the data will be overwritten

    Greg Baghdikian said:
    Is it possible assert the START pin, wait for falling DRDY edge to initiate DMA transfer, and set the SPI clock speed at just the right frequency so that all channel data is valid, deassert START, then wait until the next desired sampling period?

    I'm not entirely sure what you are suggesting here, can you elaborate?

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 130 points
    Bryan Lizon86 said:
    I'm not entirely sure what you are suggesting here, can you elaborate?

    Basically, can I run the DMA/SPI at a speed such that, every time the DRDY line goes low, the DMA/SPI happens to be transmitting/receiving the correct number of bytes per sample? Essentially watching for the first DRDY falling edge, and pulling all the channel data off of the ads1258 in an "open loop" fashion (not watching for the subsequent DRDY edges until all channels have been captured).

    This is all in an attempt to use DMA-controlled SPI.

    Bryan, do you have any recommendations on getting the ADS1258 working with a DMA-controlled SPI? Or are there other similarly capable ADCs out there that are DMA-friendly?

  • 0 in reply to Greg Baghdikian
    TI__Mastermind 47091 points

    Hi Greg Baghdikian,

    Thanks for clarifying, this might be possible. Basically you can

    • toggle the START pin and keep it high so the ADC continues looping through the sequencer
    • wait for DRDY to drop low the first time
    • send the RDATA command, and ensure the STATUS byte is enabled. This requires 40 SCLKs (8-bit for RDATA, 8-bit for STATUS, and 24-bit for ADC data)
    • Continue sending this same frame (40-bits) until you get all data from however many channels are enabled in the sequencer
    • Ensure that you are clocking out multiple complete 24-bit values between DRDY toggling, as some of them will be corrupted or not new data. I would suggest setting the SCLK speed so you clock out at least two complete frames in each conversion period
    • Use the DRDY bit in the STATUS byte to determine which data is new, and used the CHID bits to determine which channel you are measuring in that frame

    I tried this on the EVM, see below. I am only showing two frames worth of data, but I had all 16 single-ended channels enabled and I was operating at 23.7kSPS.

    Let me know if you have any questions about this information

    In parallel, I will have one of colleagues reach out to you for more info on a new part that might fit your needs

    -Bryan

  • +1 in reply to Bryan Lizon86
    TI__Mastermind 47091 points

    Hi Greg Baghdikian,

    See below for an additional plot showing all 16x DRDY transitions (actually 17x)

    I also added a WREG at the end to just rewrite the MUXSG0 register to 0xFF (so no change), but this resets the sequencer channel index back to the first enabled channel. I was having issues with this setup where if I didn't read the exact right amount of information, I could wind up on an unknown step in the sequence. This ensures that you always start at the beginning

    I also was able to toggle START to control conversions

    Let me know if you have any questions about this setup, and if this is the type of solution you were after

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 130 points

    Hi Brian,

    Thanks for trying this out and for the instructions.This would probably work for us, however I'd still be interested in hearing from your colleague about other potential options from TI.

    For example, I've worked in the past with the AD7949 from Analog, where the sampling, sequencing and transactions are all controlled by the SPI signaling, making it trivial to interface with a DMA-controlled SPI interface.

    -Greg

  • 0 in reply to Greg Baghdikian
    TI__Mastermind 47091 points

    Hi Greg Baghdikian,

    Thanks, I have pinged them again to reach out to you

    -Bryan