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ADS9224R: Issue with data protocol. ADC sending code 0 periodically.

Didier Goulet Tran
Prodigy 10 points
Part Number: ADS9224R

Tool/software:

Hello,

I'm currently trying to interface an ADS9224R with a STM32. I believe I'm there but it seems I have a little issue with the codes from the ADS9224. The weird thing is that it seems to be inconsistent.

I generate all the signals for the SDI protocol using timers from the STM32. It seems to be quite consistent here is an example:

As you can see I believe everything is well conditioned. The clock is between 16 and 20 ns.

Now the output seems to be good. It follows the wave generated from the wave form generator: In this case a 3kHz wave

The issue seems to be those dips to 0 that are quite synchronized. Here are the codes sent out during those dips.

I have set the READY_MASK in the register OUTPUT_DATA_WORD_CFG.

I dont understand where those small 8 to 12 ns pulses comes from.

Sometimes I get glitches on the clock like so:

But most of the 0 dip seems to be due to an other thing. They are very consistent in the wave form happening always at the same place.

I am currently using external cables to link the ADS2944 devboard to the STM devboard, but I believe if the cables were at fault the dips would be random and not always at the same place.

Would anyone have some clues that I could verify or understands what is going on here?

The power supply seems to be good, the refout, refby2 seems to be A-okay.

  • 0
    TI__Intellectual 2390 points

    Hello Didier, 

    Welcome to the TI E2E forum! 

    I have some follow up questions on the configuration:

    • What protocol is the ADS9224R configured to? It appears that it is with Bus Width set to 4 (Quad) and with Single Data Rate, could you confirm?
    • What is the SPI SCLK frequency? How much does the clock and duty cycle fluctuate?
      • In the 1st screenshot shared the 1st cycle had a 25MHz SCLK with ~50% duty cycle, but the 2nd one had a 27.7MHz SCLK with about a 44% duty cycle (this gets close to the tPH_CLK low limit. 
    • What is the voltage on DVDD and what is the SMT digital level set to as well as the logic analyzer used to capture the screenshots shared?

    If Refout and Refby2 look good then it seems like the glitches might be happening at around ~2.5V, which is also interesting. Has there been any modifications on the ADS9224REVM? Do you have any scope shots of what the input signal looks like before the ADC?

    Best regards, 

    Yolanda