ADS52J90: Not able to read registers through SPI

Trushal Alshi

Part Number: ADS52J90

Tool/software:

We are trying to write to ADS52J90. Following datasheet guidelines for SPI write and read, checked set up and hold conditions on oscilloscope.

Following commands are written in sequence

1) Reset ADC 0 >> 1 >> 0

2) Write 0x3000 to address 0x0A ( to Initialize the chip)

3) Write 0x0060 to address 0x01 (to enable JESD)

4) Write 0x0002 to address 0x00 (Enable SPI Read)

5) Read from address 0x00 . This readback always gives 0xFFFF i.e. MOSI always remains high. In simulation, we had hold MISO to '1' Hence it shows 0xFFFF for the sake of demonstration.

We made sure that the ADC has 60 Mhz System clock before reset step 1) . PDN_GLOBAL = 0V, PDN_FAST = 0V and SPI_DIG_EN = 1.8V We never had chance to work with evaluation board of ADS52J90.

SPI clock around 32 Khz.

Thanks,

Trushal

8 months ago

0 Trushal Alshi 8 months ago

Prodigy 140 points

The Simulation image is RTL simulation. It is just to verify if the CS, CLK and SDIN sequence for SPI write is correct. I will share the oscilloscope screenshot soon. Is there any way to check if the chip is running after reset apart from SPI read. Unfortunately we have not taken out test points from LVDS pins in prototype pcb as intended use was only JESD. It would help if someone shares a C code or config file to put ADC though initialization and JESD mode.

+1 Sachin H K 8 months ago in reply to Trushal Alshi

TI__Expert 7725 points

Hi,

Can you please try reading other register ?

To verify the write is working properly you can measure current in reset state and do global powerdown and measure the current again.

0 Trushal Alshi 8 months ago in reply to Sachin H K

Prodigy 140 points

HI Sachin,

Thanks for the reply. Yes things are working for me, Able to read back from other registers. Now the issue is when I clear the READ enable, i.e. writing 0x0000 to address 0x00, looks like the chip reset and previous written values when read enabled again, reads 0xFFFF. I have one more query regarding JESD. After writing 0x060 to 0x01 (Enable JESD and Disable LVDS), does the JESD start start sending immediately if SYS_REF clock input starts. We are integrating the ADC with TI JESDC IP. Does it require JESD version change in ADC register address 0x55

Thanks,

Trushal

0 Trushal Alshi 8 months ago in reply to Trushal Alshi

Prodigy 140 points

Hi Sachin,

My issue is resolved. Thanks for the support. More accurate reason for the failure was damaged RESET pin of the ADC. I guess we had damaged the RESET pin of ADC by mistakenly connecting to 3.3V domain, cause of that the RESET was always pulled high. I appreciate your keen support.

Thanks,

Trushal