ADS127L18: Digital interface MCU

Hello Stas,

It is possible the F28P65X family can support the ADS127L18 at maximum data rate over 8 channels.  Operating DCLK at 65.536MHz will allow TDM of 2 channels on a single DOUT lane at the maximum data rate.  Using a 4-lane interface, along with the F28P65X Configurable Logic Blocks should, in theory, be able to support this, but to my knowledge, no one as developed any specific code to prove this is possible.

We are working on example code that allows using the AM6411 Sitara processor family with integrated PRU (Programmable Real-time Unit) to implement a full parallel interface, supporting full throughput of the ADS127L18.  I am not sure what the status of this project is and will need to get back to you regarding this effort.

As a side note, we do provide example FPGA code to implement the full parallel interface if you decide to use an FPGA in your system.

Regards,
Keith Nicholas
Precision ADC Applications

Hi!

Thanks, for advice

I prefer MCU based architecture as simple to start

If no MCU based solution from TI with parallel interface controller I think I will prefer some STM32H7 with FMC.

I prefer not to start FPGA, I see it as next level of complexity.

And processor based architecture is definitely most complex solution.

Hi!

Thanks!

I selected this adc for high sample rate and delta-sigma for it's integrating/precise nature.

Maybe I am wrong, but here is my application:

I have 600VDC driver for 3-phase sensorless motor.

I need to estimate position of rotor at startup (Lq !=Ld)

So I make small pulse (we estimate it should be like 4V avg)

And so really small duty cycle of PWM and quite noisy

Let's assume we control it with 10 kHz so 100uS*4/600 = 800nS width.

I want to measure integral of voltage, current is not a big problem - it is high dV/dt, not dI/dt.

Now I have as option integrator on opamp + SAR in f28p65

But I think that ADS127L18 may give me better precision for this startup moment and also later in regular motor FOC.

What do you think?

Hello Stas,

The ADS127L18 is not suited to measuring 800ns pulses as you have shown above, due to the internal digital filter, which will have a maximum bandwidth of about 300kHz in the highest speed mode.  It would be a great option to measure the integrated value after the TIA stage.

I am not that familiar with the signals that need measured for FOC, but if you need to measure the peak values of the pulses, you would be limited to pulse widths of 10us or longer for good measurements (in the fastest speed mode, you could go as low as 5us, but resolution of the reading is reduced quite a bit at this speed).  These limitations again are due to the settling time of the internal digital filter.  You can think of this as an initial conversion time after a step change in the input voltage.

Regards,
Keith

Thanks Keith!

I thought that delta-sigma ADC is based on integrator.

And in continuous mode it is continuous integration with no integration window delay.

Yes later it comes to digital filter, but I thought it comes after integration.

And this latency time is just delay of "filter conveyor" like you have delay in ARM with "code conveyor".

And if it is just delay - ok I have 3uS to loose on filter 1uS on data transfer and 1uS on processing data.

Considering my maximum PWM frequency is 50kHz and I want to update FOC before next cycle I have 20uS for total delay - I am ok with 5 uS delay.

Please fix me if I am wrong!

Hello Stas,

Yes, there is an integrator in the front-end modulator but the frequency response is not the same as a simple single-stage integrator. In addition, the ADC is not continuously integrating the input signal; the input is sampled at a rate of 16.384MHz when using maximum speed mode. It is this sampled signal that is ultimately integrated and then converted to a digital code value. Maybe this will work in your system, but I am not certain the response will be equivalent to a continuous, analog integration stage, followed by an ADC.

Also, the SINC filter will delay the signal by about 4 data rate periods; the exact times are the latency times provided in Table 7-3.  Yes, if you are ok with a 5us delay due to the digital filter, then you may be able to use this.

Regards,
Keith

Do you have some reference design of such an integrator?

I see there is a problem with null for integrator, because even 0 signal will always have some offset.

Also I need to clear integrator time-to-time to avoid saturation.

Maybe there is some IC that has this solution inside?

Maybe this IC is specialized on something different, but integration is just a feature (like some smart AFE)

I am sure I am not the first one who needs to integrate signal.

I believe it may be something like "true rms detector" 

Oh, thank you so much for your effort!

I expected different behavior.

I really wanted to avoid such opamp design.

Because I expect many troubles with accuracy due to capacitors 5% usually best and at 1MHz is is a good question how close they are to capacitors.

And also I expect many troubles with drift because of middle point of sensors is not really middle point of 0V and integrator must be resettled to avoid saturation.

Also I though about these solutions (with true RMS):

ADS7028 from TI - ADC with true RMS 

https://www.ti.com/product/ADS7028

AD8361 from AD (sorry didn't find something like this from you) - true RMS detector - gives analog Vrms output https://www.analog.com/en/products/ad8361.html

I personally do like AD solution, because I can put it on hot side before AMC33xx (350kHz BW) and be sure to pass it.

I guess I can extract Vavg from Vrms. Or you think it would not work?

Thanks!