Other Parts Discussed in Thread: ADS127L18
Tool/software:
We are evaluation integration of ADS127L18 with STM32H7 microcontroller and have not got correct sample rates when ADS127L18 is configured via SPI registers.
Any hints what has not noticed would be Wellcome.
More detailed description below:
--
Our test system contains:
- ADS127L18evm board
- STM32H743nucloeo board
- Laboratory power supply
- Signal generator
- A circuit to convert single ended AC signal to symmetric one.
- One or two PCs.
- some jumper and SMA cables
Testing has been done in three phases.
1§ Verifying signal path, amplitude and quality with ADS127L18evm alone, it’s own microcontroller board and PC software by Texas.
PCM data extracted for further analysis (quality is good as expected).
Worked fine, some bugs in the PC software and restart+USB dis-/reconnect needed always if laptop went into sleep
2§ Verifying ADC data reception (SAI bus in STM32 terminology)
ADS127L18evm configured and controlled with the same microcontroller board and Texas PC software as above.
SAI (FSYNC, DCLK, D0 i.e. single data line) connected parallel via the pin header on the ADS127L18 board.
After some tweaking of the STM32H7 firmware the reception started to work - but just max 2s blocks (with 512Ksps)
at a time due the limitation of the Texas microcontroller board
3§ Configuration and control by STM32H7
- two sets of configurations:
- 512Ksps single channel, 32bit data frames including status byte
- 64Ksps dual channel, 32bit data frames including status byte
- Configuration and control via SPI (i.e. not with GPIO lines not touched after initial boot-up)
- MODE line set to 1 with pull-up setting
- XRESET set from 0 to 1 after a short delay at STM32H7 start-up
- START line tied low with a jumper on ADS127L18evm board
- SPI connected: SCLK, MISO, MOSI and XCS
- XCS low during every operation (single write etc), high othervice
- relatively low SPI CLK 1MHz, SPI mode 1
- SPI write seems to work due start/stop bits in the CONTROL registers work as expected
- 32bit data frames with status byte as requested (and which is not the default value).
- Initialization written to ADS127L18 and SAI reception initialized with a command from ethernet
- ADS127L18 initializations over SPI seen at the bottom of this text.
Expected result was to get sampling started at requested sample rate and ADC data flow from SAI,
STM32H7 firmware collects the samples to UDP/IP packets and send them to the ethernet
At phase 2 the data flow from the SAI to UDP packets worked as expected.
At phase 3 we have seen only a small constant sample rate of 256 sps instead of requested 512Ksps.
Changing channel 0 OSR setting does not affect the sample rate - as it should.
DCLK is requested 16MHz, but FSYNC is just about 256Hz. ADC data seen as short pulses every 4ms.
ADC data seen in the D0 seems to be OK, status byte is 8, what is expected value, range of the samples is reasonable,
just the sample rate is too slow.
SPI configuration register writes verified against register values shown by the Texas PC software at phase 1 or 2,
some small differences, meaning of those bits verified and should not affect.
// Set reset bit in the control register
ratError ratSpiReset()
{
// table 8-8 in datasheet
ratError retVal = ratSpiWriteAds127Reg(CONTROL, 0b01011000);
if(retVal == RAT_ERROR_NONE) {
osDelay(300);
// ADS127 sets some status bits on reset
// TODO verify them with debugger
uint8_t status = 0;
retVal = ratSpiStatus(&status);
}
return retVal;
}
// Set start bit in the control register
ratError ratSpiStart()
{
return ratSpiWriteAds127Reg(CONTROL, 0b10);
}
// Initialize ADS127
ratError ratSpiInit(uint16_t sampleRate)
{
ratError retVal = ratSpiReset();
retVal |= ratSpiWriteAds127Reg(GEN_CFG1, 0); // default
retVal |= ratSpiWriteAds127Reg(GEN_CFG2, 0b00000110); // fclk 32.768Hz instead of internal 25.6MHz
retVal |= ratSpiWriteAds127Reg(GEN_CFG3, 0b10000000); // full output slew rate in SAI, comment out for default slower one
retVal |= ratSpiWriteAds127Reg(DP_CFG1, 0b01000000); // data port status byte enabled, one data lane
// DP_CFG2 is mode depending
// CLK_CFG is mode depending
// GPIO registers are at default values (low disabled outputs)
// CHn_CFG1 default values (normal polarity, normal range, buffers disabled
// CH0_CFG2 and CHN1_CFG2 are mode depending
retVal |= ratSpiWriteAds127Reg(CH2_CFG2, 0b00100000); // power down
retVal |= ratSpiWriteAds127Reg(CH3_CFG2, 0b00100000); // power down
retVal |= ratSpiWriteAds127Reg(CH4_CFG2, 0b00100000); // power down
retVal |= ratSpiWriteAds127Reg(CH5_CFG2, 0b00100000); // power down
retVal |= ratSpiWriteAds127Reg(CH6_CFG2, 0b00100000); // power down
retVal |= ratSpiWriteAds127Reg(CH7_CFG2, 0b00100000); // power down
// CHn offsets and gains at default values 0 offset 1.0 gain
switch(sampleRate) {
case 512: // 512Ksps, one channel
retVal |= ratSpiWriteAds127Reg(DP_CFG2, 0b00100000); // DCLK is 32.768/2
retVal |= ratSpiWriteAds127Reg(CLK_CFG, 0b00001001); // ext clock, div by 2
retVal |= ratSpiWriteAds127Reg(CH0_CFG2, 0b00000000); // OSR32
retVal |= ratSpiWriteAds127Reg(CH1_CFG2, 0b00100001); // power down, using only CHN0
break;
case 64:// 64Kbps, two channels
retVal |= ratSpiWriteAds127Reg(DP_CFG2, 0b01100000); // DCLK is 32.768/8
retVal |= ratSpiWriteAds127Reg(CLK_CFG, 0b00001100); // ext clock, div by 8
retVal |= ratSpiWriteAds127Reg(CH0_CFG2, 0b00000000); // OSR32 - but should we use higher OSR and smaller clock dividers?
retVal |= ratSpiWriteAds127Reg(CH1_CFG2, 0b00000000); // OSR32 - same note as above
break;
default:
retVal |= RAT_ERROR_ARG;
}
if(retVal == RAT_ERROR_NONE) {
ratSpiStart();
}
osDelay(300);
return retVal;
}
