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ADC128S102-SEP: ADC128S102-SEP Digital Input Power Sequencing

Part Number: ADC128S102-SEP

Tool/software:

Hello,

Section 7.3.3 of the datasheet states that "The inputs are not prone to latch-up and can be asserted before the digital supply (VD) without any risk.".

However, in section 6.1 (Absolute Maximum Ratings), the 'Voltage on digital input and digital output pins to DGND" specifies a max of Vd + 0.3V.  This seems to contradict with the statement from 7.3.3.

The specific reason why I am inquiring is for the case where VD is 0V but the SPI signals are at 3.3V.  I want to ensure i will not cause an issue here or conduct through any steering diodes.

  • Hi Aidan,

    There is no requirement to power up the digital supply before the digital inputs are applied to my knowledge. The overvoltage protection diodes on the analog inputs are not present on the digital inputs, so you can follow section 7.3.3. 

    EDIT: The digital IO pins do share the same protection circuitry with the digital supply.

    Regards,
    Joel

  • Hi Joel, thank you for your response.  Since we need to be 100% sure this is the case, can you check with someone who knows.  If what you say is true, then it seems the absolute maximum rating section needs to be revised.

  • Hi Aidan,

    Sure I'll follow up with more information.

    Regards,
    Joel

  • Hi Aidan,

    I wasn't able to get anyone to assure that violating the absolute maximum would be okay. Given that, I suggest making sure that the SPI signals are only present on the digital inputs when DVDD is also present. I'll keep trying to determine what exactly is causing that rating to be there.

    Regards,
    Joel

  • Joel, thank you for continuing to look into this.  It is still relevant for us and would be great to know.

  • Hi Aidan,

    I was able to take a look at this a little more this week. The digital IO pins actually do share the same protection circuitry of that of the digital supply, so the absolute max ratings should be followed. I've marked the section of the datasheet you pointed out initially as something that needs updating for the next revision, and edited my initial response above to point to the correct answer.

    As a side note, would you be open to having a conversation on your use case of the ADC128S102-SEP over email?

    Regards,
    Joel