ADC10D1500: Performance Plots of ADC with Balun in Q-Channel

Hi Santanu,

Please provide a bit more detail on your request.

What sampling rate? What analog input Fin frequencies? Any other special register writes?

Anything else?

Thanks,

Rob

Hi Rob, 

Sampling rate at 1350 MHz, Analog Input Frequency : 750 MHz, 1000 MHz & 1250 MHz @ -1 dBFS

ADC Configuration : Pin Control Mode, 1:2 Demux Non-DES

Default register values. 

Looking for ENOB, SNR, SINAD & SFDR prformance plots. 

Thanks & Regards,

Santanu KUmar SInha

Hi Santanu,

Thank you for the details. I will get this to you early next week.

Regards,

Rob

Hi Rob,

Thank you for the Information.

I have a query related to placement of Balun and AC-Coupling capacitor for Sampling clock for this ADC.

As per the recommendation in "Schematic Layout and guidelines" document, we should be placing the above close to ADC. However, due to placement constraint, a differential trace length of approx. 2516 Mils from AC coupling capacitor to ADC_CLK+/- Pins is feasible.

Is the above placement fine or any improvement needs to be done ?

Thanks and Regards,

Santanu Kumar Sinha

Hi Santanu,

Just so I understand, The balun will "drive" the sampling clock inputs from 2.5inches away. Think this will be fine, what is the balun and what is the single-ended amplitude level at the primary of the balun? And do you have a means to increase the level if needed?

Also, I would put the a 100ohm DIFF termination resistor near the ADC as well in your setup. This will help with reflections due to the long traces from the balun.

Regards,

Rob

Hi Rob,

I have used the same Balun recommended in guidelines i.e. "B0430J50100A00". The max input power at primary of the Balun would be 5.78 dBm single ended. I have an option to decrease the level if needed.

As I understand from above, I have to include a 100 ohm DIFF Termination near ADC to reduce reflections.

Where should I place the DIFF Temination i.e. After AC-coupling capacitor or before AC-coupling capacitor ?

Sequence of placement in current test setup is PLL - Filter - Balun - AC coupling capacitor - "Long Trace 2.5 inch" - ADC.

Thanks & Regards,

Santanu Kumar Sinha

Hi Santanu,

I would make the sequence as follows:

PLL - filter - AC cap - balun - AC cap - long trace - diff term (close to ADC) - ADC.

I would use the max level into the Balun as you can for the clock. This will maximize the slew and minimize the jitter on the clocking edge.

Also, for the data you wanted collected originally, I don't have a PC old enough to use on this EVM.

The Wavevision data collection SW has never been updated and does not work on current PC/Windows systems.

If you can wait a week or so, I can have our CM run the data.

Please advise.

Regards,

Rob

Hi Rob, 

Thanks for providing the requested performance plots. Sampling Frequency 1500 MHz is also fine to me. 

Do we have to invert the ADC samples data in FPGA for the above configuration of Balun in Q Channel ? Please confirm.

Thanks and Regards

Santanu Kumar Sinha

Hi Rob,

Thank you for addressing my queries.

I hope the above captured test data @ 1500 MHz includes inversion of adc samples in FPGA. 

Correct me if I am going wrong. 

Thanks and Regards,

Santanu Kumar Sinha

Hi Rob, 

I am referring to plus and minus of the baluns secondary line up to the Q channel input is inverted. In this case, the captured ADC data is inverted in FPGA before giving input to WaveVision Software.

The "fold back" on Nyquist zone is understood from the captured fft waveform snapshots. 

I hope we are on the same page. 

Thanks and Regards,

Santanu Kumar SInha