Other Parts Discussed in Thread: DAC38J84
Tool/software:
Hi,
We are trying to operate DAC38J84EVM, in 12.5 Gbps line rate, with FPGA clock = 312.5 MHz, and DAC Clock = 2500 MHz (x4 interpolation) . But we are not getting the linkup , with DAC Errors as 0x70b, stating 8b/10b disparity errors, 8b/10b Not in Table errors, CGS Errors. Also the SERDES FIFO are not operating as required despite correct SERDES clocks and DAC JESD Clocks. Hence, we wanted to look into equalization capabilities of DAC38J84. We tried looking into the registers mentioned in the specs for DAC Equalizations, but were unable to get it figured out. Currently, value of config61 ( 0x3D) is 0x88 . So , we would like to know how can we approach to see if our Equalization settings in DAC JESD Side is appropriate or not. Also, We tried finding Equalization settings in DAC GUI but did not find anything, did we miss something ?
Please let us know if we can provide any other info.
