ADC3663: SLVDS to LVDS in Data Pin and Clock Pin

Yishan Chen

Intellectual 1890 points

Part Number: ADC3663
Other Parts Discussed in Thread: SN65LVDS100

Tool/software:

Hi Team,

Customer are testing with our ADC3663 connecting with Xilinx 7035.

They are considering the different voltage standard between ADC3663 datasheet and FPGA datasheet about SLVDS and LVDS

I have see some E2E question regarding the signal standard, but I am not sure if we need a translator or we can directly connect ADC3663 and FPGA.

DCLKIN usage

FPGA can output a signal with 1 to 1.425V VCM which typical value is 1.2V and 247 to 600mV which typical value is 350mV VOD to ADC3663

ADC3663 input specification is 1-1.3V with 1.2V typical value and 200 to 650 mVpp VOD with typical value 350mVpp

Data Lane

ADC3663 can output 1.0VCM with 500 to 850mVpp VOD.

FPGA can receive 0.3-1.425V with typical value 1.2V and 100mV to 600mV VOD

My question is:

How to understand the input VCM and VOD in ADC3663, Is that means we can accept any VCM voltage between 1 and 1.3V and VOD between 200 to 650mV, How ADC3663 recognize High and low signal?

Could ADC3663 directly connect with FPGA? Or we need some AC coupling+Bias method or translator?

Thank you,

Yishan Chen

over 1 year ago

0 Yishan Chen over 1 year ago

TI__Intellectual 1890 points

Add few more question:

1. mVpp in datasheet means the peak to peak value in VOD? For example, 700mV means 1+0.35V and 1-0.35V in DA pin?

2.Do we have 100ohom terminal resistor or Bias in DCLKIN?

3.Could ADC3663 DCLK PIN withstand 1.425+0.6V and 1.425-0.6V VCM and VOD?

0 Rob Reeder over 1 year ago in reply to Yishan Chen

TI__Mastermind 45670 points

Hi Chen,

The ADC3663 can be directly interfaced to the FPGA with any LVDS IO bank. Please make sure the 100ohm differential terminations are enabled.

For the DCLKIN, you need to provide the common mode bias to drive these inputs. A simple SN65LVDS100 LVDS translator, driver will do.

Regards,

Rob

0 Yishan Chen over 1 year ago in reply to Rob Reeder

TI__Intellectual 1890 points

Hi Rob,

Thank you for your conclusion.

By the way, could you please help me understand the question i raised above?

Thank you,

Yishan Chen

0 Rob Reeder over 1 year ago in reply to Yishan Chen

TI__Mastermind 45670 points

Hi Yishan,

You had many questions..... Please let me know specifically your question.

Regards,

Rob

0 Yishan Chen over 1 year ago in reply to Rob Reeder

TI__Intellectual 1890 points

please check below question:

1. mVpp in datasheet means the peak to peak value in VOD? For example, 700mV means 1+0.35V and 1-0.35V in DA pin?

2.Do we have 100ohom terminal resistor or Bias in DCLKIN?

3.Could ADC3663 DCLK PIN withstand 1.425+0.6V and 1.425-0.6V VCM and VOD?

4.Why Data lane can directly connect but DCLK need bias?

Thank you,

Yishan Chen

0 Rob Reeder over 1 year ago in reply to Yishan Chen

TI__Mastermind 45670 points

Hi Yishan,

1: yes, correct

2, no 100 ohms needed, yes DCLKIN bias needed, see the EVM schematic as a guide

3: DCLKIN needs bias, DCLK would connect to FPGA the same as data lanes

Thanks,

Rob

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ADC3663: SLVDS to LVDS in Data Pin and Clock Pin