• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 97 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS127L01: Strange erroneous readings from ADC

John Fahey
Prodigy 20 points
Part Number: ADS127L01

Tool/software:

Hello!

I have created a circuit board which uses the ADS127L0 in the following circuit:

Note that I have previously had an issue with this circuit because I missed the connection from pin6 to VCC and from pin28 to VCC to keep it enabled. I have fixed this manually but it is not reflected in the schematic. 

As far as specifics go, note that the chip shares a common VCC and GND for the AVDD/DVDD and AGND/DGND. The filter and OSR pins are set in a way that it is running in low latency/2048x oversampling. This is because when i have a different filter and osr setting, the problem i am about to describe becomes worse.

Basically, when i plot the data from the ADC, i get occasional spikes when it should be a constant:

Note that I am plotting the raw value from the ADC here. 

another example:

I have ensured that I am in the correct SPI mode, and am waiting for the DRDY pin to go low before polling for the data. This problem gets significantly worse (more spikes per 100 samples) for a lower OSR or a different filter, or if i decrease the delay in my main loop in code. 

Due to this, it makes me believe it is a timing related issue, but per the datasheet i am using an spi clock of 2MHz which falls well within the range of acceptable values for a 3V power supply, and i am using the correct SPI mode. I am waiting for DRDY to go low before making a measurement, and i am delaying my loop by 1ms.

Is this likely to be a timing issue? If so, how can i fix it? or have i somehow damaged my ADC while soldering (note I have two which exhibit the same behavior)

Thanks!

  • 0
    TI__Mastermind 46140 points

    Hello John,

    The ADS127L01 SCLK idles low, launches data on the SDO pin on the SCLK rising edge, and captures data on the SDI pin on the falling edge.  You may want to confirm that your SPI port is configured to capture data on the SCLK falling edge.   This is the most common description of SPI mode 01, but some processor families have a slightly different definition.

    Yes, this could be a timing issue, or simply a signal integrity issue.  You will need to use an oscilloscope to measure the /DRDY, /CS, SCLK, SDO to confirm both timing and clean signals.  If you could include an image of 2 full sequential frames with these signals, this will help to confirm.  (Also, SDI should be held low when reading conversion results.)

    Regards,
    Keith Nicholas
    Precision ADC Applications